MAX4731 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX4731 Datasheet PDF : 14 Pages
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50Ω, Dual SPST Analog Switches in UCSP
Test Circuits/Timing Diagrams (continued)
MAX4731
MAX4732
MAX4733
VN_
NO_
OR NC_
V+
V+
COM_
LOGIC
INPUT
IN_
GND
RL
300Ω
VOUT
CL
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
RL
VOUT = VN_ ( RL + RON )
Figure 2. Switching Time
LOGIC VIH
INPUT
VIL
SWITCH
OUTPUT
0V
tr < 5ns
tf < 5ns
50%
tOFF
VOUT 0.9 x VOUT
0.9 x VOUT
tON
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
MAX4733
V+
VN_
NO1
NC2
V+
COM1
COM2
IN1
LOGIC
INPUT
IN2
GND
VOUT2
RL2
300Ω
CL2
35pF
VOUT1
RL1
CL1
300Ω
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 3. Break-Before-Make Interval (MAX4733 only)
V+
LOGIC
INPUT
0V
SWITCH
OUTPUT 1
(VOUT1) 0V
SWITCH
OUTPUT 2
(VOUT2)
0V
tr < 5ns
tf < 5ns
50%
0.9 x V0UT1
0.9 x VOUT2
tBBM
tBBM
MAX4731
MAX4732
MAX4733
VGEN
RGEN
NC_
OR NO_
GND
V+
V+
COM
IN_
VIL TO VIH
Figure 4. Charge Injection
VOUT
CL
1nF
VOUT
IN
OFF
∆VOUT
OFF
ON
ON
OFF
OFF
IN
Q = (∆VOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
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