MAX3420EECJ(2005) Ver la hoja de datos (PDF) - Maxim Integrated
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MAX3420EECJ Datasheet PDF : 23 Pages
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USB Peripheral Controller
with SPI Interface
mode, these status bits are accessed in the normal
way, as register bits.
The first five registers (R0–R4) access endpoint FIFOs.
To access a FIFO, an initial command byte sets the
register address and then consecutive reads or writes
keep the same register address to access subsequent
FIFO bytes.
The remaining registers (R5–R20) control the operation
of the MAX3420E. Once a register address above R4 is
set in the command byte, successive byte reads or
writes in the same SPI access cycle (SS low) increment
the register address after every byte read or written. This
incrementing operation continues until R20 is accessed.
Subsequent byte reads or writes continue to access
R20. Note that this auto-incrementing action stops with
the next SPI cycle, which establishes a new register
address. Addressing beyond R20 is ignored.
Table 1. MAX3420E Register Map
REG NAME
b7
b6
b5
b4
b3
b2
R0 EP0FIFO
b7
b6
b5
b4
b3
b2
R1 EP1OUTFIFO
b7
b6
b5
b4
b3
b2
R2 EP2INFIFO
b7
b6
b5
b4
b3
b2
R3 EP3INFIFO
b7
b6
b5
b4
b3
b2
R4 SUDFIFO
b7
b6
b5
b4
b3
b2
b1
b0
acc
b1
b0 RSC
b1
b0 RSC
b1
b0 RSC
b1
b0 RSC
b1
b0 RSC
R5 EP0BC
R6 EP1OUTBC
R7 EP2INBC
R8 EP3INBC
R9 EPSTALLS
R10 CLRTOGS
0
0
0
0
0
EP3DISAB
b6
b6
b6
b6
ACKSTAT
EP2DISAB
b5
b5
b5
b5
STLSTAT
EP1DISAB
b4
b3
b2
b4
b3
b2
b4
b3
b2
b4
b3
b2
STLEP3IN STLEP2IN STLEP1OUT
CTGEP3IN CTGEP2IN CTGEP1OUT
b1
b1
b1
b1
STLEP0OUT
0
b0 RSC
b0 RSC
b0 RSC
b0 RSC
STLEP0IN RSC
0
RS C
R11 EPIRQ
R12 EPIEN
R13 USBIRQ
R14 USBIEN
0
0
SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ IN0BAVIRQ RC
0
0
SUDAVIE IN3BAVIE IN2BAVIE OUT1DAVIE OUT0DAVIE IN0BAVIE RSC
URESDNIRQ VBUSIRQ NOVBUSIRQ SUSPIRQ URESIRQ BUSACTIRQ RWUDNIRQ OSCOKIRQ RC
URESDNIE VBUSIE NOVBUSIE SUSPIE URESIE BUSACTIE RWUDNIE OSCOKIE RSC
R15 USBCTL
R16 CPUCTL
R17 PINCTL
R18 REVISION
R19 FNADDR
R20 IOPINS
HOSCSTEN VBGATE
0
0
EP3INAK EP2INAK
0
0
0
b6
GPIN3
GPIN2
CHIPRES
0
EP0INAK
0
b5
GPIN1
PWRDOWN CONNECT
0
0
FDUPSPI INTLEVEL
0
0
b4
b3
GPIN0 GPOUT3
S IG RWU
0
POSINT
0
b2
GPOUT2
0
0
GPXB
1
b1
GPOUT1
0
RS C
IE
RS C
GPXA RSC
0
R
b0
R
GPOUT0 RSC
Note: The acc (access) column indicates how the SPI Master can access the register.
R = Read, RC = Read or Clear, RSC = Read, Set, or Clear.
Writing to an R register (Read-Only) has no effect.
Writing a 1 to an RC bit (Read or Clear) clears the bit.
Writing a zero to an RC bit has no effect.
6 _______________________________________________________________________________________
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