MAX3204E(2004) Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

MAX3204E
(Rev.:2004)

Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD Protection Arrays for High-Speed Data Interfaces

Maxim Integrated 

Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD

Protection Arrays for High-Speed Data Interfaces

Detailed Description

The MAX3202E/MAX3203E/MAX3204E/MAX3206E are

diode arrays designed to protect sensitive electronics

against damage resulting from ESD conditions or tran-

sient voltages. The low input capacitance makes these

devices ideal for high-speed data lines. The

MAX3202E, MAX3203E, MAX3204E, and MAX3206E

protect two, three, four, and six channels, respectively.

The MAX3202E/MAX3203E/MAX3204E/MAX3206E are

designed to work in conjunction with a device’s intrinsic

ESD protection. The MAX3202E/MAX3203E/MAX3204E/

MAX3206E limit the excursion of the ESD event to

below ±25V peak voltage when subjected to the

Human Body Model waveform. When subjected to the

IEC 61000-4-2 waveform, the peak voltage is limited to

±60V when subjected to Contact Discharge and ±100V

when subjected to Air-Gap Discharge. The device that

is being protected by the MAX3202E/MAX3203E/

MAX3204E/MAX3206E must be able to withstand these

peak voltages plus any additional voltage generated by

the parasitic board.

Applications Information

Design Considerations

Maximum protection against ESD damage results from

proper board layout (see the Layout Recommendations

section and Figure 2). A good layout reduces the para-

sitic series inductance on the ground line, supply line,

and protected signal lines.

The MAX3202E/MAX3203E/MAX3204E/MAX3206E ESD

diodes clamp the voltage on the protected lines during

an ESD event and shunt the current to GND or VCC. In

an ideal circuit, the clamping voltage, VC, is defined as

the forward voltage drop, VF, of the protection diode

plus any supply voltage present on the cathode.

For positive ESD pulses:

VC = VCC + VF

For negative ESD pulses:

VC = -VF

In reality, the effect of the parasitic series inductance

on the lines must also be considered (Figure 1).

For positive ESD pulses:

VC

=

VCC

+

VF(D1)

+

L1 x

d(IESD)

dt





+

L2

x

d(IESD

dt

)





For negative ESD pulses:

VC

=

−





VF(D2)

+ L1 x

d(IESD)

dt





+

L3

x

d(IESD )

dt









where IESD is the ESD current pulse.

POSITIVE SUPPLY RAIL

L2

D1

L1

I/O_

PROTECTED

LINE

D2

L3

GROUND RAIL

Figure 1. Parasitic Series Inductance

VCC

L1

PROTECTED LINE

NEGATIVE ESD

CURRENT

PULSE

PATH TO

GROUND

GND

L2

D1

I/O_

D2

L3

VC

PROTECTED

CIRCUIT

Figure 2. Layout Considerations

4 _______________________________________________________________________________________

Share Link: