MAX2101CMQ Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

MAX2101CMQ

6-Bit Quadrature Digitizer

Maxim Integrated 

6-Bit Quadrature Digitizer

Filter Temperature Compensation

In both techniques discussed above, the ratio RF/RTC deter-

mines the compensation required to produce a

filter response with 0TC. As noted in the VPTAT vs.

Temperature graph in the Typical Operating Characteristics,

this ratio should be set at 0.8.

Baseband Offset Correction

The MAX2101 integrates a high level of RF signal pro-

cessing, and applies substantial gain from the IF inputs

to the baseband signals applied to the ADC. Offset in

the signal path can seriously decrease the compo-

nent’s dynamic range, and variation in offset between I

and Q channels can seriously degrade overall receiver

performance. Several circuit design techniques are

used to minimize offset within the chip. However, two

characteristics of the component contribute to offset in

the signal path.

The off-chip tank network for the VCO resonates the LO

frequency with a relatively large amplitude. If the LO

couples into the IF input, the coupled LO will mix down

to a DC value, which depends on the AGC setting. This

DC signal manifests itself as an offset in the baseband

signal. The second source of offset is the active low-

pass anti-aliasing filters. This offset depends on the

cutoff frequency. These two elements represent the

major contributors to DC offset in the signal path.

Offset Adjust Pins OFFI, OFFQ

The MAX2101 offers an offset adjust pin for each of the

I and Q channels, labeled OFFI and OFFQ, respective-

ly. The offset adjust input exhibits an adjustment range

that is sufficient to correct for the errors mentioned

above. The polarity of the OFF_ input is such that a

positive change of the OFF_ voltage results in a nega-

tive transition in the baseband signal, BBOUT_. The off-

set adjust range compensates for up to 5LSBs of offset.

A feedback-controlled, offset-correction network can

be realized that will null any offset detected in the base-

band signal applied to the ADCs. The differential base-

band signal is sampled at the input to the ADC and

integrated over a sufficiently large period of time (deter-

mined by the minimum frequency of the baseband sig-

nal), extracting the offset signal. This error signal is

internally applied to the OFF_ input, completing the

feedback loop. The MAX2101 integrates the op amps

and 150kΩ pickoff resistors of the offset correction net-

work. Figure 10 shows a simplified schematic diagram

of the network. Simply connect the appropriate capaci-

tors as shown in Figure 11.

The network in Figure 11 is a lowpass filter with a 5Hz

cutoff frequency. The user can tailor the cutoff frequency

by choosing the appropriate value of capacitance,

according to the following relation:

C=

1

2πfO (150kΩ)

where:

C = integrator capacitance

for cutoff frequency

Frequency components of the baseband signal near or

below the cutoff frequency will interfere with the opera-

tion of this network. Fortunately, the compressed and

encoded nature of baseband signals at this stage of

the signal chain in typical applications will insure mini-

mal low-frequency components. Hence, this technique

will eliminate all offsets, independent of AGC setting, fil-

ter cutoff frequency, or changes in ambient tempera-

ture.

Pin 68, ENOPB, is normally connected to ground.

Pulling ENOPB to VCC disables the op amps, thus

opening the servo loop, and disabling offset correction.

The baseband pins (6, 7, 74, 75) should be left uncon-

nected, or buffered with a high-impedance load (resis-

tive load greater than 10kΩ and capacitive load less

than 3pF).

Sample Clock Generation

The master sample clock (MCLK) input for the

MAX2101 is typically driven by a low-noise, low-drift

crystal oscillator. The signal should be between 0dBm

and +10dBm, and must be AC coupled to the MCLK

input. This signal is buffered and divided according to

the programmable sample-rate prescaler (PSRP). The

actual sample rates are binary weighted divisors of the

MCLK frequency. Program the sample rates with pins

S0, S1, and S2, as shown in Table 1.

Table 1. Sample-Rate Control

S2 S1 S0 Sample Rate

Description

000

fc/ 1

001

fc/2

Full Sample Rate

Div–2 Sample Rate

010

fc/4

Div–4 Sample Rate

011

fc/8

Div–8 Sample Rate

100

fc/8

Div–8 Sample Rate

101

fc/16

Div–16 Sample Rate

110

111

fc/32

fc/64

Div–32 Sample Rate

Div–64 Sample Rate

Note: The inputs S0, S1, and S2 are not latched.

______________________________________________________________________________________ 15

Share Link: