M95128-DW6P/V Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

M95128-DW6P/V

128 Kbit Serial SPI bus EEPROM with high speed clock

STMicroelectronics 

Instructions

M95128, M95128-W, M95128-R

5.5

Read from Memory Array (READ)

As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven

Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data

Input (D). The address is loaded into an internal address register, and the byte of data at

that address is shifted out, on Serial Data Output (Q).

If Chip Select (S) continues to be driven Low, the internal address register is automatically

incremented, and the byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a

single READ instruction.

The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip

Select (S) signal can occur at any time during the cycle.

The first byte addressed can be any byte within any page.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 9. Read from Memory Array (READ) sequence

S

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

C

Instruction

16-Bit Address

D

15 14 13 3 2 1 0

MSB

High Impedance

Q

Data Out 1

Data Out 2

76543 2107

MSB

AI01793D

1. The most significant address bits (b15, b14) are Don’t Care.

20/41

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