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JEDEC
Symbol
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
Std
Symbol
tRC
tACC
tCE
tOE
tDF
tDF
tOH
Parameter
Read cycle time
Address to output delay
Chip enable to output
Output enable to output
Chip enable to output High Z
Output enable to output High Z
Output hold time from addresses,
CE or OE, whichever occurs first
-55
-70
-90
-120
-150
Min Max Min Max Min Max Min Max Min Max Unit
55 - 70 - 90 - 120 - 150 - ns
- 55 - 70 - 90 - 120 - 150 ns
- 55 - 70 - 90 - 120 - 150 ns
- 25 - 30 - 35 - 50 - 55 ns
- 15 - 20 - 20 - 30 - 35 ns
- 15 - 20 - 20 - 30 - 35 ns
0 - 0 - 0 - 0 - 0 - ns
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Rising input
Falling input
Undefined / don’t care
5HDG#ZDYHIRUP
Addresses
CE
OE
tRC
Addresses stable
tACC
tDF
tOE
WE
Outputs
tCE
tOH
High Z
Output valid
High Z
45
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