M65580MAP-XXXFP
Function and Outline of ASIC Block
Chip
Power down mode:
Service SW:
3 modes [PD0 & PD1 & PD2]
stop of Vertical (Vramp) output (For cutoff adjustment)
Analog Block
• Input stage ⇒ CVBS & Y/C input signals
Input level (CVBS): 1.23 Vp-p (173 IRE) @max. / 1.0 Vp-p @typ.
Input level (Y/C):
Y: 1.00 Vp-p (140 IRE) @typ. / C: 0.7 Vp-p @typ.
• Output stage ⇒ RGB output signals
Output level:
0.7 Vp-p (typ.)
Drive (R & G & B): –3 to +4 dB by 7 bit (White Balance)
Cutoff (R & G & B): 0.5 V by 9 bit (Start lighting point)
Digital Block
• 2DYCS
Adaptive YC separation by using of 1H line memory and original algorithm
• Luminance processing
Contrast:
0 to 200 LSB by 7 bit
Brightness:
–20 to 20 LSB by 8 bit (Pedestal DC level)
Sharpness:
0 to 3 dB by 5 bit (by 0, 70, 140, 210 ns)
Delay adjustment: 0 to 210 ns by 2 bit (70 ns step) to Chroma signal
Black-stretch:
3 selectable stretch point
[Stretch areas (0 to 25/30/40 IRE), through areas (25/30/40 IRE ∼)]
4 selectable black-stretch curves (1/4, 2/4, 3/4, 4/4)
• Chroma processing
Tint:
–45 to 45 degree by 7 bit ⇒ about 0.7 degree
Variable demodulator (R-Y) axis
(–22.5 to +22.5 degree by 6 bit ⇒ about 0.7 degree)
Color:
0 to 200% by 7 bit
• RGB matrix
ACL:
Matrix (R-Y signal) ratio selectable (12/8, 13/8, 14/8)
Automatic Contrast Limiter by MCU port (ADC) and I2C bus
EXT/RGB:
clip to 7 LSB @ data < 0Fh
BlueBack:
ON/OFF selectable
Mute:
ON/OFF of R/G/B output
Neck Protector:
R/G/B output to zero (no signal)
Deflection Block
• Horizontal Output
AFC2 phase:
Hold ⇒ Shut down:
AFC1 gain:
• Vertical Output
V position:
V size:
Linearity:
+5 to –5 µs by 5 bit
fh@Hold-down: in about 16.5 kHz ⇒ fh@Shutdown: H-STOP
Normal/High selectable for VTR skew
0 to 16 H by 3 bit ⇒ 2H unit (connected with BLK)
1.4 to 2.6 V by 7 bit
0 to 30% by 7 bit
REJ03F0184-0201 Rev.2.01 Mar 31, 2008
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