M50FW040K5P Ver la hoja de datos (PDF) - STMicroelectronics

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componentes Descripción

Fabricante

M50FW040K5P

4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory

STMicroelectronics 

M50FW040

Signal descriptions

2.1.5

2.1.6

2.1.7

2.1.8

2.1.9

Interface configuration (IC)

The Interface Configuration input selects whether the Firmware Hub (FWH) or the

Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be

selected before power-up or during a Reset and, thereafter, cannot be changed. The state

of the Interface Configuration, IC, should not be changed during operation.

To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to

float or driven Low, VIL; to select the Address/Address Multiplexed (A/A Mux) Interface the

pin should be driven High, VIH. An internal pull-down resistor is included with a value of RIL;

there will be a leakage current of ILI2 through each pin when pulled to VIH; see <Blue>Table

18.

Interface Reset (RP)

The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is

set Low, VIL, the memory is in Reset mode: the outputs are put to high impedance and the

current consumption is minimized. When RP is set High, VIH, the memory is in normal

operation. After exiting Reset mode, the memory enters Read mode.

CPU Reset (INIT)

The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves

identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Clock (CLK)

The Clock, CLK, input is used to clock the signals in and out of the Input/Output

Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification.

Top Block Lock (TBL)

The Top Block Lock input is used to prevent the Top Block (Block 7) from being changed.

When Top Block Lock, TBL, is set Low, VIL, Program and Erase operations in the Top Block

have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is

set High, VIH, the protection of the Block is determined by the Lock Register. The state of

Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to 6).

Top Block Lock, TBL, must be set prior to a Program or Erase operation is initiated and must

not be changed until the operation completes or unpredictable results may occur. Care

should be taken to avoid unpredictable behavior by changing TBL during Program or Erase

Suspend.

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