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4250

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

LIST OF PRECAUTIONS

ΠNoise and latch-up prevention

Connect a capacitor on the following condition to prevent noise

and latch-up;

• connect a bypass capacitor (approx. 0.01 µF) between pins

VDD and VSS at the shortest distance,

• equalize its wiring in width and length, and

• use the thickest wire.

In the One Time PROM version, CNVSS pin is also used as

VPP pin. Connect this pin to VSS through the resistor about

5 kΩ which is assigned to CNVSS/VPP pin as close as

possible at the shortest distance.

 Prescaler

Stop the prescaler operation to change its frequency dividing

ratio.

Ž Timer count source

Stop timer 1 counting to change its count source.

 Program counter

Make sure that the PCH does not specify after the last page of

the built-in ROM.

 G0/INT pin

When the interrupt valid waveform of the G0/INT pin is changed

with the bit 2 of register K0 in software, be careful about the

following notes.

• After clear the bit 0 of register V1 to “0” (Figure 29Œ),

change the interrupt valid waveform of G0/INT pin with the

bit 2 of register K0 .

• Set a value to bit 2 of register K0 and execute the SNZ0

instruction to clear the external interrupt request flag (EXF0)

after executing at least one instruction (refer to Figure 29).

Depending on the input state of the G0/INT pin, the EXF0

flag may be set when the interrupt valid waveform is

changed.

‘ Notes on unused pins

• When pins G0/INT, G1/TOUT, G2 and G3 are connected to

VSS pin, turn off their pull-up transistors (register PU0=“!02”)

and also invalidate the key-on wakeup functions of pins

G1/TOUT, G2 and G3 (register K0=“!!0!2”) by software.

When the POF instruction is executed while these pins are

connected to VSS and the key-on wakeup functions are left

valid, the system returns from RAM back-up state by

recognizing the return condition immediately after going into

the RAM back-up state. When these pins are open, turn on

their pull-up transistors (register PU0=“!12”) by software.

• When ports S0–S3 are connected to VSS pin, invalidate the

key-on wakeup functions (register K0=“!!!02”) by

software. When the POF instruction is executed while these

pins are connected to VSS and the key-on wakeup functions

are left valid, the system returns from RAM back-up state

by recognizing the return condition immediately after going

into the RAM back-up state.

• When ports D2/C and D3/K are connected to VSS pin, turn

off their pull-up transistors (register PU0=“0!2”) by software.

When these pins are open, turn on their pull-up transistors

(register PU0=“1!2”) by software.

(Note when connecting to VSS and VDD)

• Connect the unused pins to VSS or VDD at the shortest distance

(within 20 mm) and use the thick wire against noise.

’ Multifunction

• G0/INT pin can be also used as an I/O port G0 even when it

is used as INT pin.

• G1/TOUT pin can be also used as input port G1 even when it

is used as TOUT pin.

• D2/C pin can be also used as I/O port D2 even when it is

used as port C.

• D3/K pin can be also used as I/O port D3 even when it is

used as port K.

...

LA 4

; (!!!02)

TV1A

; The SNZ0 instruction is valid ............. Œ

LA 4

TK0A

; Change of the interrupt valid waveform

NOP

.............................................................. 

SNZ0

; The SNZ0 instruction is executed

NOP

...

! : this bit is not related to the setting of G0/INT pin.

Fig. 29 External interrupt program example

MITSUBISHI

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