M2V56S20TP Ver la hoja de datos (PDF) - Mitsumi

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Fabricante

M2V56S20TP

256M Synchronous DRAM

Mitsumi 

SDRAM (Rev.1.1)

Single Data Rate

Feb.2000

MITSUBISHI LSIs

M2V56S20/ 30/ 40/ TP -6, -7, -8

256M Synchronous DRAM

Revison History

Rev.

1.0

1.1

Date Description

July / '99 1st edition

Feb. / '00

- Remove "Power-Down" from Function Truth Table for CKE Note 2

- Modify Average Supply Current from Vdd

Icc2N, Icc3N Test Condition (/CS≥ VIHmin)

Icc3PS Limits (from 3mA to 4mA)

Icc5 Limits (from 160/150mA to 180/170mA)

Icc6 Test Condition (CKE ≤0.2V)

Icc6 Limits (from 2mA to 3mA)

- Change Switching Characteristics tAC of -8 for CL=2 from 6ns to 7ns

- Add Note to Switching Characteristics

- Change Output Load Condition to 50pF only

- Remove tCCD from AC Timing Requirements

MITSUBISHI ELECTRIC

48

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