M28F420-80N1TR Ver la hoja de datos (PDF) - STMicroelectronics
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M28F420-80N1TR Datasheet PDF : 38 Pages
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M28F410, M28F420
Table 19A. Write AC Characteristics, Chip Enable Controlled (1)
(TA = 0 to 70°C or –40 to 85°C; VPP = 12V ± 5%)
Symbol Alt
Parameter
M28F410 / 20
-70
-80
VCC = 5V ± 5% VCC = 5V ± 10%
SRAM
Interface
EPROM
Interface
tAVAV
tPHEL
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tWC
tPS
tCS
tWP
tDS
tDH
tCH
tWPH
Write Cycle Time
Power Down High to Chip Enable Low
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Data Valid to Chip Enable High
Chip Enable High to Data Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip
Enable Low
Min Max Min Max
70
80
210
210
0
0
50
50
50
50
0
0
10
10
20
30
tAVEH
tAS Address Valid to Chip Enable High
50
50
tPHHEH (5)
tPHS
Power Down VHH (Boot Block Unlock) to Chip
Enable High
100
100
tVPHEH (5)
tVPS VPP High to Chip Enable High
100
100
tEHAX
tAH Chip Enable High to Address Transition
10
10
tEHQV1 (2, 3)
Chip Enable High to Output Valid (Word/Byte
Program)
6
6
tEHQV2 (2, 3)
Chip Enable High to Output Valid (Boot Block
Erase)
0.3
0.3
tEHQV3 (2)
Chip Enable High to Output Valid (Parameter
Block Erase)
0.3
0.3
tEHQV4 (2)
Chip Enable High to Output Valid (Main Block
Erase)
0.6
0.6
tQVPH (5)
tPHH Output Valid to Reset/Power Down High
0
0
tQVVPL (5)
Output Valid to VPP Low
0
0
tPHBR (4, 5)
Reset/Power Down High to Boot Block Relock
100
100
Notes: 1. See Figure 3 and Table 8 for timing measurements.
2. Time is measured to Status Register Read giving bit b7 = ’1’.
3. For Program or Erase of the Boot Block RP must be at VHH.
4. Time required for Relocking the Boot Block.
5. Sampled only, not 100% tested.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
sec
sec
sec
ns
ns
ns
20/38
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