M25P05-AVMP6TG Ver la hoja de datos (PDF) - Numonyx -> Micron

Número de pieza

componentes Descripción

Fabricante

M25P05-AVMP6TG

512-Kbit, serial flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

Instructions

M25P05-A

6.2

Write disable (WRDI)

The write disable (WRDI) instruction (Figure 8) resets the write enable latch (WEL) bit.

The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The write enable latch (WEL) bit is reset under the following conditions:

● Power-up

● Write disable (WRDI) instruction completion

● Write status register (WRSR) instruction completion

● Page program (PP) instruction completion

● Sector erase (SE) instruction completion

● Bulk erase (BE) instruction completion.

Figure 8. Write disable (WRDI) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03750D

20/52

Share Link: