Operating features
M25P05-A
4.6
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P05-A features the following data protection mechanisms:
● Power on reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification
● Program, erase and write status register instructions are checked that they consist of a
number of clock pulses that is a multiple of eight, before they are accepted for
execution
● All instructions that modify data must be preceded by a write enable (WREN)
instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Write disable (WRDI) instruction completion
– Write status register (WRSR) instruction completion
– Page program (PP) instruction completion
– Sector erase (SE) instruction completion
– Bulk erase (BE) instruction completion
● The block protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the software protected mode (SPM)
● The Write Protect (W) signal, in co-operation with the status register write disable
(SRWD) bit, allows the block protect (BP1, BP0) bits and status register write disable
(SRWD) bit to be write-protected. This is the hardware protected mode (HPM)
● In addition to the low power consumption feature, the deep power-down mode offers
extra software protection, as all write, program and erase instructions are ignored.
Table 2. Protected area sizes
Status Register
content
Memory content
BP1 bit
0
0
1
1
BP0 bit
0
1
0
1
Protected area
Unprotected area
none
All sectors (sectors 0 and 1)
No protection against page program (PP) and sector erase (SE)
All sectors (sectors 0 and 1) protected against bulk erase (BE)
All sectors (sectors 0 and 1)
none
1. The device is ready to accept a bulk erase instruction if, and only if, both block protect (BP1, BP0) are 0.
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