LXT972A Ver la hoja de datos (PDF) - Intel

Número de pieza

componentes Descripción

Fabricante

LXT972A

3.3V Dual-Speed Fast Ethernet Transceiver

Intel 

3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A

MDIO Frame Structure

The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is

shown in Figure 3 and Figure 4 (read and write). MDIO Interface timing is shown in Table 32 on

page 53.

Figure 3. Management Interface Read Frame Structure

MDC

MDIO

(Read)

32 "1"s

0

1

1

0

A4

A3

A0

R4

R3

R0

Z0

D15 D15D14 D14D1 D1 D0

High Z

Preamble

ST

Op Code

PHY Address

Register Address

Turn

Around

Data

Idle

Write

Read

Figure 4. Management Interface Write Frame Structure

MDC

MDIO

(Write)

32 "1"s

0

1

0

1

A4

A3

A0

R4

R3

R0

1

0

D15

D14

D1

D0

Idle Preamble

ST

Op Code

PHY Address

Register Address

Turn

Around

Data

Idle

Write

3.2.3.2

3.2.3.3

MII Interrupts

The LXT972A provides a single interrupt pin (MDINT). Interrupt logic is shown in Figure 5. The

LXT972A also provides two dedicated interrupt registers. Register 18 provides interrupt enable

and mask functions and Register 19 provides interrupt status. Setting bit 18.1 = 1, enables the

device to request interrupt via the MDINT pin. An active Low on this pin indicates a status change

on the LXT972A. Interrupts may be caused by four conditions:

• Auto-negotiation complete

• Speed status change

• Duplex status change

• Link status change

Hardware Control Interface

The LXT972A provides a Hardware Control Interface for applications where the MDIO is not

desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.

Refer to Section 3.4.5, “Hardware Configuration Settings” on page 23 for additional details.

Datasheet

19

Share Link: