LX1689IPW(2003) Ver la hoja de datos (PDF) - Microsemi Corporation

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componentes Descripción

Fabricante

LX1689IPW
(Rev.:2003)

Third Generation CCFL Controller

Microsemi Corporation 

INTEGRATED PRODUCTS

LX1689

Third Generation CCFL Controller

PRODUCTION DATA SHEET

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (V_BATT)................................................................................................. 30V

Digital Input (ENABLE).....................................................................................-0.3V to 7V

Analog Inputs Transient Peak (I_SNS, OC_SNS, OV_SNS)..............................-25V to +25V

Analog Inputs (BRITE_IN, EA_IN).................................................................. -0.3V to 5.5V

Digital Inputs (DIM_CLK,DIM_MODE, DIV_248) ......................................... -0.3V to 5.5V

Digital Output (AOUT, BOUT) .................................................................-0.3V to VDD_P +0.5V

Analog Outputs (BRITE_C, I_R, BRITE_OUT, BRITE_R, EA_OUT) ...-0.3V to VDD_A_ +0.5V

Operating Temperature Range ..................................................................... -45°C – 100°C

Maximum Junction Temperature ...............................................................................125°C

Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to

Ground. Currents are positive into, negative out of specified terminal.

PACKAGE PIN OUT

GND

AOUT

BOUT

DIM_CLK

DIM_MODE

DIV_248

BRITE_C

BRITE_R

BRITE_IN

ENABLE

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

PW PACKAGE

(Top View)

VDD_P

VDD_A

V_BATT

OC_SNS

OV_SNS

I_SNS

BRITE_OUT

EA_OUT

EA_IN

I_R

THERMAL DATA

PW Plastic TSSOP 20-Pin

THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA

144°C/W

Junction Temperature Calculation: TJ = TA + (PD x θJA).

The θJA numbers are guidelines for the thermal performance of the device/pc-board

system. All of the above assume no ambient airflow.

PIN NAME

GND

VDD_P

AOUT

VDD_A

BOUT

V_BATT

FUNCTIONAL PIN DESCRIPTION

DESCRIPTION

Ground

Power VDD_P Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the

on chip VDD_P LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally 5.3V

and is used only to drive the output buffers at AOUT and BOUT. The external capacitor will be a 100 to 1000nF

ceramic dielectric. Up to 5mA DC additional load may be imposed by external circuitry. External load must be

reduced if the combination of output current and input voltage exceeds power dissipation capability of the die.

A buffer N-FET driver output. The pin includes a internal 10K pull down resistor.

Analog VDD_A Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the

on chip VDD_A LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally

2.95V and is used to drive all circuitry except the output buffers at AOUT and BOUT. Average internal load is

6mA. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the

combination of output current and input voltage exceeds power dissipation capability of the die. The external

capacitor will be a 100 to 1000nF ceramic dielectric type.

B buffer N-FET driver output. The pin includes a internal 10K pull down resistor.

Voltage Input, 3 to 28V input range. V_BATT is switched (see ENABLE) to remove power from chip. Two LDO

regulators follow the switch, one generates VDD_P (see VDD_P) and the other VDD_A (see VDD_A). Care

must be taken in power distribution design to minimize transients and noise coupling from the VDD_P output to

the VDD_A output. The external capacitor will be a 100 to 1000nF ceramic dielectric type.

Copyright  2000

Rev. 1.0b, 2003-03-31

Microsemi

Integrated Products

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

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