LVT22V10 Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Fabricante
LVT22V10 Datasheet PDF : 20 Pages
| |||
Philips Semiconductors
3V high speed, universal PLD device
Product specification
LVT22V10
Output Register Preload
The register on the LVT22V10 can be preloaded from the output
pins to facilitate functional testing of complex state machine designs.
This feature allows direct loading of arbitrary states, making it
unnecessary to cycle through long test vector sequences to reach a
desired state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper recovery. The
procedure for preloading follows:
1. Raise VCC to 3.3V ± 0.3V.
2. Set pin 2 or 3 to VHH to disable outputs and enable preload.
PRELOAD SET-UP
SYMBOL
VHH
VILP
VIHP
tD
tI/O
PARAMETER
Super-level input voltage
Low-level input voltage
High-level input voltage
Delay time
I/O valid after Pin 2 or 3 drops from VHH to VILP
3. Apply the desired value (VILP/VIHP) to all registered output pins.
Leave combinatorial output pins floating.
4. Clock Pin 1 from VILP to VIHP.
5. Remove VILP/VIHP from all registered output pins.
6. Lower pin 2 or 3 to VILP.
7. Enable the output registers according to the programmed
pattern.
8. Verify VOL/VOH at all registered output pins. Note that the output
pin signal will depend on the output polarity.
LIMITS
MIN
REC
MAX
9.5
9.5
10
0
0
0.8
2.4
3.3
3.6
100
200
1000
100
UNIT
V
V
V
ns
ns
PINS 2, 3
VHH
VILP
REGISTERED
OUTPUTS
CLOCK
tD
DATA IN
tD
tD
tD
tD
Output Register Preload Waveform
tI/O
DATA OUT
VIHP
VOH
VOL
VILP
VIHP
VILP
SP00373
1998 Feb 10
8
Share Link: 