LVT22V10 Ver la hoja de datos (PDF) - Philips Electronics
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LVT22V10 Datasheet PDF : 20 Pages
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Philips Semiconductors
3V high speed, universal PLD device
Product specification
LVT22V10
AC ELECTRICAL CHARACTERISTICS
Over commercial operating temperature range.
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
MIN
TYP MAX
UNIT
Input or feedback to non-registered output2
PLCC package
tPD
Input or feedback to non-registered output2
DIP and SOL packages
Active-LOW
Active-HIGH
Active-LOW
Active-HIGH
7.5
ns
7.5
ns
8.0
ns
8.0
ns
tS
Setup time from input, feedback or SP to Clock
tH
Hold time
tCO
Clock to output
tCF
Clock to feedback3
tAR
Asynchronous Reset to registered output
tARW
Asynchronous Reset width
tARR
Asynchronous Reset recovery time
tSPR
Synchronous Preset recovery time
tWL
Width of Clock LOW
tWH
Width of Clock HIGH
fMAX
Maximum frequency;
External feedback 1/(tS + tCO)4
Maximum frequency;
Internal feedback 1/(tS + tCF)4
tEA
Input to Output Enable5
tER
Input to Output Disable5
Capacitance6
5.5
ns
0
ns
5.0
ns
3.0
ns
12.0
ns
5.0
ns
5.0
ns
5.0
ns
3.0
ns
3.0
ns
95
MHz
118
MHz
8.5
ns
8.5
ns
CIN
COUT
Input Capacitance (Pin 1)
Input Capacitance (Others)
Output Capacitance
VIN = 2.0V
VCC = 3.3V,
6
pF
VIN = 2.0V
Tamb = 25°C,
6
pF
VOUT = 2.0V
f = 1MHz
8
pF
NOTES:
1. Test Conditions: R1 = 500Ω, R2 =500Ω
2. tPD is tested with switch S1 open and CL = 50pF (including jig capacitance). VIH = 3V, VIL = 0V, VT = 1.5V.
3. Calculated from measured fMAX internal.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
5. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.3V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.3V) level with S1 closed.
6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
1998 Feb 10
6
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