LV8041FN Ver la hoja de datos (PDF) - SANYO -> Panasonic

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Fabricante

LV8041FN

Seven-Channel Motor Driver IC for Digital Cameras

SANYO -> Panasonic 

Serial Data Input Settings

LV8041FN

ST

DATA

D0 D1

D2

D3

D4

D5

D6

D7

SCLK

STB

State setting data latched

Data is input in order from data bit 0 to data bit 7. The data is transferred on the clock signal rising edge and after all

the data has been transferred, it is latched on the rising edge of the STB signal.

x Timing with which the serial data is reflected in the output

Type 1: For the forward/reverse (FR) and drive mode (MS) settings in STP setting mode, after the data is latched,

after the clock falling edge is detected, the new settings are reflected in the output on the next rising edge

on the clock signal.

Type 2: For the reset and output enable settings, after the data is latched, the new settings are reflected in the output

on the next rising edge on the clock signal.

Type 3: For settings other than those listed above, the new settings are reflected in the output at the same time as

the data is latched with the STB signal.

CLK

STB

F/R (STP)

MS

Falling edge detection

Data latch timing

Example: 2-phase drive

Reflected on the

rising edge

Example:

4W1-2 phase drive

CLK

STB

RESET

ENABLE

Data latch timing

Example: reset

Cases other

than those shown

at the left or above

Reflected on the rising edge

Example: Reset cleared

STB signal timing

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