LTM4619 Ver la hoja de datos (PDF) - Linear Technology

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LTM4619

Dual, 26VIN, 4A DC/DC µModule Regulator

Linear Technology 

LTM4619

PIN FUNCTIONS

VIN (J1 to J3, J10 to J12, K1 to K4, K9 to K12, L1 to L5,

L8 to L12, M1 to M12): Power Input Pins. Apply input

voltage between these pins and PGND pins. Recommend

placing input decoupling capacitance directly between VIN

pins and PGND pins. For VIN < 5.5, tie VIN and INTVCC

together.

VOUT1, VOUT2 (A10 to D10, A11 to D11, A12 to D12, A1 to

D1, A2 to D2, A3 to D3): Power Output Pins. Apply output

load between these pins and PGND pins. Recommend

placing output decoupling capacitance directly between

these pins and PGND pins.

PGND (H1, H2, H4, H9, H11, H12, G1 to G12, F1 to

F5, F7 to F12, E1 to E12, D4 to D9, C4 to C9, B4 to B9,

A4 to A9): Power ground pins for both input and output

returns.

INTVCC (F6): Internal 5V Regulator Output. This pin is for

additional decoupling of the 5V internal regulator.

EXTVCC (J4): External Power Input to Controller. When

EXTVCC is higher than 4.7V, the internal 5V regulator is

disabled and external power supplies current to reduce

the power dissipation in the module. This will improve the

efficiency more at high input voltages.

SGND (J6, J7, H6, H7): Signal Ground Pin. Return ground

path for all analog and low power circuitry. Tie a single

connection to PGND in the application.

MODE/PLLIN (H8): Mode selection or external synchroniza-

tion pin. Tying this pin high enables pulse-skipping mode.

Tying this pin low enables force continuous operation.

Floating this pin enables Burst Mode operation. A clock

on the pin will force the controller into continuous mode

of operation and synchronize the internal oscillator. The

external clock input high threshold is 1.6V, while the input

low threshold is 1V.

FREQ/PLLFLTR (J8): Frequency Selection Pin. An internal

lowpass filter is tied to this pin. The frequency can be se-

lected from 250kHz to 780kHz by varying the DC voltage

on this pin from 0V to 2.4V. Leave this pin floating when

external synchronization is used.

TK/SS1, TK/SS2 (K8, K5): Output Voltage Tracking and

Soft-Start Pins. Internal soft-start currents of 1.3μA charge

the soft-start capacitors. See the Applications Information

section to use the tracking function.

VFB1, VFB2 (K7, K6): The negative input of the error

amplifier. Internally, this pin is connected to VOUT with

a 60.4k precision resistor. Different output voltages can

be programmed with an additional resistor between VFB

and SGND pins. See the Applications Information section

for details.

COMP1, COMP2 (L7, L6): Current Control Threshold and

Error Amplifier Compensation Point. The module has been

internally compensated for most I/O ranges.

PGOOD (H5): Output Voltage Power Good Indicator. Open

drain logic output that is pulled to ground when the output

voltage is not within ±7.5% of the regulation point.

RUN1, RUN2 (J9, J5): Run Control Pins. 0.5μA pull-up

currents on these pins turn on the module if these pins

are floating. Forcing either of these pins below 1.2V will

shut down the corresponding outputs. An additional 4.5μA

pull-up current is added to this pin, once the RUN pin rises

above 1.2V. Also, active control or pull-up resistors can

be used to enable the RUN pin. The maximum voltage is

6V on these pins.

SW1, SW2 (H10, H3): Switching Test Pins. These pins are

provided externally to check the operation frequency.

4619f

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