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LTC3707-SYNC

High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator

Linear Technology 

LTC3707-SYNC

APPLICATIO S I FOR ATIO

winding as shown in Figure 6a or the capacitive charge

pump shown in Figure 6b. The charge pump has the

advantage of simple magnetics.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors CB connected to the BOOST

pins supply the gate drive voltages for the topside MOSFETs.

Capacitor CB in the functional diagram is charged though

external diode DB from INTVCC when the SW pin is low.

When one of the topside MOSFETs is to be turned on, the

driver places the CB voltage across the gate-source of the

desired MOSFET. This enhances the MOSFET and turns on

the topside switch. The switch node voltage, SW, rises to

VIN and the BOOST pin follows. With the topside MOSFET

on, the boost voltage is above the input supply: VBOOST =

VIN + VINTVCC. The value of the boost capacitor CB needs

to be 100 times that of the total input capacitance of the

topside MOSFET(s). The reverse breakdown of the exter-

nal Schottky diode must be greater than VIN(MAX). When

adjusting the gate drive level, the final arbiter is the total

input current for the regulator. If a change is made and the

input current decreases, then the efficiency has improved.

If there is no change in input current, then there is no

change in efficiency.

Output Voltage

The IC output voltages are each set by an external feedback

resistive divider carefully placed across the output capaci-

tor. The resultant feedback signal is compared with the

internal precision 0.800V voltage reference by the error

amplifier. The output voltage is given by the equation:

VOUT

=



0.8V1+

R2

R1

where R1 and R2 are defined in Figure 2.

SENSE+/SENSE– Pins

The common mode input range of the current comparator

sense pins is from 0V to (1.1)INTVCC. Continuous linear

operation is guaranteed throughout this range allowing

output voltage setting from 0.8V to 7.7V, depending upon

the voltage applied to EXTVCC. A differential NPN input

stage is biased with internal resistors from an internal

2.4V source as shown in the Functional Diagram. This

requires that current either be sourced or sunk from the

SENSE pins depending on the output voltage. If the output

voltage is below 2.4V current will flow out of both SENSE

pins to the main output. The output can be easily preloaded

by the VOUT resistive divider to compensate for the current

comparator’s negative input bias current. The maximum

current flowing out of each pair of SENSE pins is:

ISENSE+ + ISENSE– = (2.4V – VOUT)/24k

Since VOSENSE is servoed to the 0.8V reference voltage, we

can choose R1 in Figure 2 to have a maximum value to

absorb this current.

OPTIONAL EXTVCC

CONNECTION

5V < VSEC < 7V

VIN

+

CIN

VIN

LTC3707-SYNC

TG1

N-CH

EXTVCC

SW

T1

1:N

R6

FCB

BG1

R5

SGND

PGND

N-CH

VSEC

+

RSENSE

1µF

VOUT

+

COUT

3707 F06a

VIN

+

CIN

VIN

LTC3707-SYNC

TG1

N-CH

EXTVCC

SW

BG1

PGND

N-CH

+

1µF

BAT85

0.22µF

BAT85

VN2222LL

RSENSE

L1

+

BAT85

VOUT

COUT

3707 F06b

Figure 6a. Secondary Output Loop & EXTVCC Connection

18

Figure 6b. Capacitive Charge Pump for EXTVCC

3707sf

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