LTC1860LCS8 Ver la hoja de datos (PDF) - Linear Technology

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LTC1860LCS8

µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP

Linear Technology 

LTC1860L/LTC1861L

TEST CIRCUITS

Load Circuit for tdDO, tr, tf, tdis and ten

TEST POINT

3k

SDO

20pF

VCC tdis WAVEFORM 2, ten

tdis WAVEFORM 1

1860 TC01

Voltage Waveforms for ten

CONV

SDO

1860 TC03

ten

Voltage Waveforms for SDO Delay Times, tdDO and thDO

SCK

VIL

tdDO

thDO

SDO

VOH

VOL

1860 TC02

Voltage Waveforms for SDO Rise and Fall Times, tr, tf

SDO

tr

VOH

VOL

tf

1860 TC04

Voltage Waveforms for tdis

CONV

VIH

SDO

WAVEFORM 1

(SEE NOTE 1)

90%

tdis

SDO

WAVEFORM 2

(SEE NOTE 2)

10%

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL

1860 TC05

APPLICATIO S I FOR ATIO

LTC1860L OPERATION

Operating Sequence

The LTC1860L conversion cycle begins with the rising

edge of CONV. After a period equal to tCONV, the conver-

sion is finished. If CONV is left high after this time, the

LTC1860L goes into sleep mode drawing only leakage

current. On the falling edge of CONV, the LTC1860L goes

into sample mode and SDO is enabled. SCK synchronizes

the data transfer with each bit being transmitted from SDO

on the falling SCK edge. The receiving system should

capture the data from SDO on the rising edge of SCK. After

completing the data transfer, if further SCK clocks are

applied with CONV low, SDO will output zeros indefinitely.

See Figure 1.

8

Analog Inputs

The LTC1860L has a unipolar differential analog input. The

converter will measure the voltage between the “IN+” and

“IN–” inputs. A zero code will occur when IN+ minus IN–

equals zero. Full scale occurs when IN+ minus IN– equals

VREF minus 1LSB. See Figure 2. Both the “IN+” and

“IN–” inputs are sampled at the same time, so common

mode noise on the inputs is rejected by the ADC. If “IN–”

is grounded and VREF is tied to VCC, a rail-to-rail input span

will result on “IN+” as shown in Figure 3.

Reference Input

The voltage on the reference input of the LTC1860L (and

the LTC1861L MSOP package) defines the full-scale range

of the A/D converter. These ADCs can operate with refer-

ence voltages from VCC to 1V.

18601Lf

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