LTC1860LCS8 Ver la hoja de datos (PDF) - Linear Technology

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LTC1860LCS8

µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP

Linear Technology 

LTC1860L/LTC1861L

PI FU CTIO S

LTC1861L (MSOP Package)

CONV (Pin 1): Convert Input. A logic high on this input

starts the A/D conversion process. If the CONV input is left

high after the A/D conversion is finished, the part powers

down. A logic low on this input enables the SDO pin,

allowing the data to be shifted out.

CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must

be free of noise with respect to AGND.

AGND (Pin 4): Analog Ground. AGND should be tied

directly to an analog ground plane.

DGND (Pin 5): Digital Ground. DGND should be tied

directly to an analog ground plane.

SDI (Pin 6): Digital Data Input. The A/D configuration

word is shifted into this input.

SDO (Pin 7): Digital Data Output. The A/D conversion

result is shifted out of this output.

SCK (Pin 8): Shift Clock Input. This clock synchronizes the

serial data transfer.

VCC (Pin 9): Positive Supply. This supply must be kept

free of noise and ripple by bypassing directly to the

analog ground plane.

VREF (Pin 10): Reference Input. The reference input de-

fines the span of the A/D converter and must be kept free

of noise with respect to AGND.

LTC1861L (SO-8 Package)

CONV (Pin 1): Convert Input. A logic high on this input

starts the A/D conversion process. If the CONV input is left

high after the A/D conversion is finished, the part powers

down. A logic low on this input enables the SDO pin,

allowing the data to be shifted out.

CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must

be free of noise with respect to GND.

GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.

SDI (Pin 5): Digital Data Input. The A/D configuration

word is shifted into this input.

SDO (Pin 6): Digital Data Output. The A/D conversion

result is shifted out of this output.

SCK (Pin 7): Shift Clock Input. This clock synchronizes the

serial data transfer.

VCC (Pin 8): Positive Supply. This supply must be kept

free of noise and ripple by bypassing directly to the

analog ground plane. VREF is tied internally to this pin.

W

FUNCTIONAL BLOCK DIAGRA

VCC

CONV (SDI) SCK

IN+

(CH0)

IN –

(CH1)

GND

CONVERT

CLK

BIAS AND

SHUTDOWN

SERIAL

SDO

PORT

DATA IN

+

12-BIT

SAMPLING

–

ADC

12-BITS

DATA OUT

VREF

PIN NAMES IN PARENTHESES REFER TO LTC1861L

1860L/61L BD

18601Lf

7

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