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Fabricante

LTC1266

Synchronous Regulator Controller for N- or P-Channel MOSFETs

Linear Technology 

UU W U

APPLICATIO S I FOR ATIO

600

VOUT = 3.3V

500

TOPSIDE

400 P-CHANNEL

TOPSIDE

N-CHANNEL WITH

CHARGE PUMP

LTC1266

LTC1266-3.3/LTC1266-5

100

Burst Mode OPERATION

ENABLED

90

300

200

TOPSIDE N-CHANNEL

100

WITH POWER VIN = 12V

0

0

1

2

3

4

5

LOAD CURRENT

1266 F05

Figure 5. Comparison of Dropout Performance

VIN

R2

–

R1

+

LTC1266

LBOUT

1.25V

REFERENCE

1266 F06

Figure 6. Low-Battery Comparator

The divided down voltage at the “–” input to the comparator

is compared to an internal 1.25V reference. This reference

is separate from the 1.265V reference used by the voltage

comparator and current comparator for regulation and is

not disabled by the shutdown pin, therefore the low-battery

detection is operational even when the rest of the chip is

shut down. The comparator is functional down to an input

voltage of 2.5V. Thus, the output will provide a valid state

even when the rest of the chip does not have sufficient

voltage to operate. For best performance, the value of the

pull-up resistor should be high enough that the output is

pulled down to ground when sinking 200µA or less.

Suppressing Burst Mode Operation

Normally, enabling Burst Mode operation is desired due to

its superior efficiency at low load currents (see Figure 7).

However, in certain applications it may be desirable to

inhibit this feature. Some reasons for doing so are:

1. To eliminate audible noise from certain types of induc-

tors at light loads.

80

Burst Mode OPERATION

INHIBITED

70

60

0.01

0.1

1

LOAD CURRENT (A)

5

1266 F07

Figure 7. Effect of Disabling Burst Mode Operation on Efficiency

2. If the load is never expected to drop low enough to

benefit from the efficiency advantages of Burst Mode

operation, the output capacitor ESR and minimum capaci-

tance requirements (which may falsely trigger Burst Mode

operation if not met) can be relaxed if Burst Mode opera-

tion is disabled.

3. If an auxiliary winding is used. Disabling Burst Mode

operation guarantees switching independent of the load

on the primary. This allows power to be taken from the

auxiliary winding independently.

4. Tighter load regulation (< 1%).

Burst Mode operation is disabled by applying a CMOS

logic high voltage (> 2.1V) to Pin 4. When it is disabled, the

voltage comparator limit is raised high enough so that it no

longer is involved in regulation; however it is still active

and is useful as a voltage clamp to keep the output from

overshooting.

Note that since the inductor current must reverse to

regulate the output at zero load when Burst Mode opera-

tion is disabled, the minimum inductance (LMIN) specified

during Inductor Core Selection is no longer applicable.

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in DC (resistive) load

current. When a load step occurs, VOUT shifts by an

amount equal to ∆ILOAD (ESR), where ESR is the effective

series resistance of COUT. ∆ILOAD also begins to charge or

13

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