LT5528
APPLICATIO S I FOR ATIO
Additionally, the exposed pad provides heat sinking for the
part and minimizes the possibility of the chip overheating.
If improved LO and Image suppression are required, an LO
feed-through calibration and an Image suppression calibra-
tion can be performed. The evaluation board schematic
of the calibration hardware, the calibration procedure and
the results are described in an application note.
R1 (optional) limits the Enable pin current in the event
that the Enable pin is pulled high while the VCC inputs are
low. In Figures 8, 9, 10 and 11, the silk screens and the
PCB board layout are shown.
Figure 8. Component Side Silk Screen of Evaluation Board
Figure 9. Component Side Layout of Evaluation Board
Figure 10. Bottom Side Silk Screen of Evaluation Board
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Figure 11. Bottom Side Layout of Evaluation Board
5528f