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LT5524EFE

Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain

Linear Technology 

LT5524

APPLICATIO S I FOR ATIO

In fixed gain applications, the LT5524 can be set to 3dB

attenuation relative to maximum gain. As shown in the

Typical Performance Characteristics, this gives a 2dB

reduction in the output noise floor with no loss of linearity.

In general, the output noise floor can be reduced by

decreasing ROUT (and hence power gain), at the cost of

reduced OIP3.

LT5524 Characterization

The LT5524’s typical performance data are based on the

test circuits shown in Figures 9 and 10. Figure 9 does not

necessarily reflect the use of the LT5524 in an actual

application. (For that, see the Application Boards section.)

Rather, it represents a compromise that most accurately

measures the actual operation of the part by itself,

undistorted by the artifacts of the impedance transformation

network, or by external bandwidth limiting factors. Balun

transformers are used to interface with single-ended test

equipment. Input and output resistive attenuators (not

shown) provide broadband I/O impedance control. The

L1, L2 inductors are selected for maximally flat AC output

response. COUT (normally open) shows the placement of

capacitive loading when this is specified as a

characterization variable. The VCCO monitor pin allows

setting the output DC level (5V typical) by adjusting

voltage VOSUP.

VCC

RSRC

50Ω

VSRC

C1

0.33µF

T1

1:1

R9

35.7Ω

C7

47nF

R10

35.7Ω

R7

35.7Ω

C8

47nF

R8

35.7Ω

ETC-1-

1-13

ATT =

7.7dB

C2

0.1µF

LT5524

IN+ –

DUT

IN– +

R5 R6

51k 51k

COUT

(OPT)

ROUT

COUT

(OPT)

PGA0 PGA1 PGA2 PGA3

VCCO

MONITOR

L1

(OPT)

L2

(OPT)

R1 R2

25Ω 25Ω

R3

37.4Ω

R4

37.4Ω

C4

0.1µF

C5

47nF

C6

47nF

C3

4.7µF

T1

1:1

VOSUP

RLOAD

50Ω

ROUT R3, R4 ATT L1, L2

100Ω 37.4Ω 9dB 0Ω

200Ω 87.4Ω 12dB 33nH

ETC-1-

1-13

5524 F09

Figure 9. Characterization Board (Simplified Schematic)

VCC

C2

EN

0.1µF

1

20

EN

NC

NC

2

19

IF

IN

T1

3 VCC1

GND

VCC2 18

GND

1:2

4

LT5524

17

GND

GND

5 IN+

6 IN–

OUT– 16

OUT+ 15

ROUT

100Ω

7

14

J1

0Ω TC2-1T

C1

0.47µF

GND

8

GND

9

PGA0

GND

13

GND

12

PGA3

10

11

PGA1

PGA2

RMATCH

255Ω

C4

0.1µF

T2

4:1

••

•

VOSUP

C3

4.7µF

IF

OUT

RLOAD

50Ω

J2

TC4-1W

0Ω

TRANSFORMER DEMO BOARD

PGA0 PGA1

PGA2 PGA3

5524 F10

Figure 10. Output Transformer Application Board (Simplified Schematic)

5524f

13

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