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LT3050MPMSE

100mA, Linear Regulator with Precision Current Limit and Diagnostic Outputs

Linear Technology 

LT3050 Series

PIN FUNCTIONS

REF/BYP (Pin 1): Bypass/Soft-Start. Connecting a single

capacitor from this pin to GND bypasses the LT3050’s

reference noise and soft-starts the reference. A 10nF by-

pass capacitor typically reduces output voltage noise to

30μVRMS in a 10Hz to 100kHz bandwidth. Soft-start time

is directly proportional to the REF/BYP capacitor value.

If the LT3050 is placed in shutdown, REF/BYP is actively

pulled low by an internal device to reset soft-start. If low

noise or soft-start performance is not required, this pin

must be left floating (unconnected). Do not drive this pin

with any active circuitry. Because the REF/BYP pin is the

reference input to the error amplifier, stray capacitance at

this point should be minimized. Special attention should

be given to any stray capacitances that can couple external

signals onto the REF/BYP pin producing undesirable output

transients or ripple. A minimum REF/BYP capacitance of

100pF is recommended.

IMIN (Pin 2): Minimum Output Current Programming

Pin. This pin is the collector of a PNP current mirror that

outputs 1/200th of the power PNP load current. This pin

is also the input to the minimum output current fault com-

parator. Connecting a resistor between IMIN and GND sets

the minimum output current fault threshold. For detailed

information on how to set the IMIN pin resistor value,

please see the Operation section.

A small external decoupling capacitor (10nF minimum)

is required to improve IMIN PSRR. If minimum output

current programming is not required, the IMIN pin must

be left floating (unconnected).

FAULT (Pin 3): Fault Pin. This is an open collector logic

pin which asserts during current limit, thermal limit or

a minimum current fault condition. The maximum low

logic output level is defined for sinking 100μA of current.

Off state logic may be as high as 45V without damaging

internal circuitry regardless of the VIN used.

SHDN (Pin 4): Shutdown. Pulling the SHDN pin low puts

the LT3050 into a low power state and turns the output

off. Drive the SHDN pin with either logic or an open collec-

tor/drain with a pull-up resistor. The resistor supplies the

pull-up current to the open collector/drain logic, normally

several microamperes, and the SHDN pin current, typi-

cally less than 2μA. If unused, connect the SHDN pin to

IN. The LT3050 does not function if the SHDN pin is not

connected. The SHDN pin cannot be driven below GND

unless tied to the IN pin. If the SHDN pin is driven below

GND while IN is powered, the output may turn on. SHDN

pin logic cannot be referenced to a negative rail.

IN (Pin 5,6): Input. These pins supply power to the device.

The LT3050 requires a local IN bypass capacitor if it is

located more than six inches from the main input filter

capacitor. In general, battery output impedance rises

with frequency, so adding a bypass capacitor in battery

powered circuits is advisable. A minimum input of 1μF

generally suffices.

OUT (Pin 7,8): Output. These pins supply power to the

load. Stability requirements demand a minimum 2.2μF

ceramic output capacitor to prevent oscillations. Large

load transient applications require larger output capaci-

tors to limit peak voltage transients. See the Applications

Information section for details on transient response and

reverse output characteristics. Permissible output voltage

range for the adjustable voltage version is 600mV to 44.5V.

The top of the resistor divider setting output voltage in

the fixed 3.3V and 5V versions connects directly to OUT

on the IC.

ADJ (Pin 9): Adjust. This pin is the error amplifier’s inverting

terminal. Its typical bias of 16nA current flows out of the

pin (see curve of ADJ Pin Bias Current vs. Temperature

in the Typical Performance Characteristics section). The

typical ADJ pin voltage is 600mV referenced to GND.

GND (PIN 10, Exposed Pad Pin 13): Ground. The exposed

pad of the DFN and MSOP packages is an electrical con-

nection to GND. To ensure proper electrical and thermal

performance, solder Pin 13 to the PCB ground and tie

directly to Pin 10. Connect the bottom of the output volt-

age setting resistor divider directly to GND (Pin 10) for

optimum load regulation performance.

IMAX (Pin 11): Precision Current Limit Programming

Pin. This pin is the collector of a current mirror PNP that

is 1/200th the size of the output power PNP. This pin is

also the input to the current limit amplifier. Current limit

threshold is set by connecting a resistor between the IMAX

pin and GND.

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