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LT1956

High Voltage, 1.5A, 500kHz Step-Down Switching Regulators

Linear Technology 

LT1956/LT1956-5

APPLICATIO S I FOR ATIO

RFB

INPUT

RHI

C2

RLO

LT1956

IN

SHDN

2.38V

+

5.5µA

–

+

0.4V

–

GND

VSW

STANDBY

TOTAL

SHUTDOWN

L1

OUTPUT

+

C1

1956 F04

Figure 4. Undervoltage Lockout

bypassed with a 1000pF capacitor to prevent coupling

problems from the switch node. If hysteresis is desired in

the undervoltage lockout point, a resistor RFB can be

added to the output node. Resistor values can be calcu-

lated from:

[ ] RHI

= RLO

VIN − 2.38(∆V/VOUT + 1) + ∆V

2.38 − RLO (5.5µA)

( ) RFB = (RHI) VOUT/∆V

25k suggested for RLO

VIN = Input voltage at which switching stops as input

voltage descends to trip level

∆V = Hysteresis in input voltage level

Example: output voltage is 5V, switching is to stop if input

voltage drops below 12V and should not restart unless

input rises back to 13.5V. ∆V is therefore 1.5V and

VIN␣ =␣ 12V. Let RLO = 25k.

[ ( ) ] 25k 12 − 2.38 1.5/5 + 1 + 1.5

RHI =

( ) 2.38 – 25k 5.5µA

( ) 25k 10.41

=

= 116k

2.24

( ) RFB = 116k 5/1.5 = 387k

16

SYNCHRONIZING

The SYNC input must pass from a logic level low, through

the maximum synchronization threshold with a duty cycle

between 10% and 90%. The input can be driven directly

from a logic level output. The synchronizing range is equal

to initial operating frequency up to 700kHz. This means

that minimum practical sync frequency is equal to the

worst-case high self-oscillating frequency (570kHz), not

the typical operating frequency of 500kHz. Caution should

be used when synchronizing above 662kHz because at

higher sync frequencies the amplitude of the internal slope

compensation used to prevent subharmonic switching is

reduced. This type of subharmonic switching only occurs

at input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufficient slope compensa-

tion. Application Note 19 has more details on the theory

of slope compensation.

At power-up, when VC is being clamped by the FB pin (see

Figure 2, Q2), the sync function is disabled. This allows the

frequency foldback to operate in the shorted output con-

dition. During normal operation, switching frequency is

controlled by the internal oscillator until the FB pin reaches

0.8V, after which the SYNC pin becomes operational. If no

synchronization is required, this pin should be connected

to ground.

1956f

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