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LT1619

Low Voltage Current Mode PWM Controller

Linear Technology 

LT1619

APPLICATIO S I FOR ATIO

Increasing Ramp Compensation While Synchronizing

The LT1619 is synchronized by forced discharge of the

internal timing ramp. The timing ramp amplitude de-

creases as the synchronization frequency increases. Since

the internal compensation ramp is derived from the timing

ramp, reduced timing ramp results in diminished com-

pensating ramp. If the LT1619 is synchronized at frequen-

cies 20% to 30% higher than the free-running frequency,

external ramp compensation will be required. Figures 12

and 13 show two such schemes.

In both figures the compensating ramps are kept linear by

making R11-C1 and R14-C2 products substantially higher

than the synchronizing period. The compensation ramps,

1

CLK

S/S

8

VIN

2

FB

7

DRV

LT1619

3

6

VC

GATE

4

5

GND SENSE

R11

100k

D2

1N4148

C1

220pF

MAIN POWER

TRANSISTOR

Q1

2N2222

R12

2200Ω

R13

51Ω

RSENSE

1619 F12

Figure 12. Increasing Ramp Compensation. Q1 Buffers the C1

Ramp. D2 Discharges C1. Values Shown are for 10V Gate Drive

and 15mV Ramp Across R13 at 90% Duty Cycle and 500kHz

1

CLK

S/S

8

VIN

2

FB

7

DRV

LT1619

3

6

VC

GATE

4

5

GND SENSE

D2

1N4148

C2

2.2nF

R14

8200Ω

D3

1N4148

R15

2400Ω

R13

51Ω

RSENSE

1619 F13

Figure 13. Externally Increasing Ramp Compensation. Similar

to Figure 12 Except That C2 is Not Buffered with Transistor

whose peak amplitudes are made between 1/4 to 1/3 of the

current limit threshold, are developed across R13. As a

result, the effective current limit threshold is reduced by

the sum of the compensating ramp and the offset voltage

developed across R13 due to the SENSE pin input bias

current (see Figure 5). Moreover, the current limit thresh-

old becomes duty cycle dependent.

PC Board Layout and Other Practical Considerations

The following is recommended for PC board layout:

1. Trace lengths of the branches carrying switched cur-

rent should be kept short. For example, in the boost

converter of Figure 1, the circuit loop formed by M1,

RSENSE, D1 and COUT carries switched current. The size

of this loop must be minimized. RSENSE and COUT

should be grounded to a single point on a large ground

plane. This reduces switching noise and overall con-

verter jitter. It is also preferable to ground the input

capacitor C1 close to the common point between COUT

and RSENSE although this is less important.

2. Keep the trace between the sense resistor and the

SENSE pin short. When sensing high switch current,

Kelvin connection to RSENSE is necessary.

3. Bypass both the VIN and DRV pins with ceramic capaci-

tors next to the IC and the ground plane.

4. Keep high voltage switching nodes, such as the drain

and gate of the MOSFET, away from the FB and VC pins.

5. Use inductor so that its ripple current is between 1/4

and 1/3 of its peak current. Steeper inductor current

ramp results in sharper PWM comparator switching,

hence less jitter.

6. In most cases, filtering the current sense signal is not

necessary for jitter-free operation.

Figure 14 is the PC board layout for the 5V/8A and 12V/5A

boost converters shown in Figures 15a and 16a.

12

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