LPC2212 Ver la hoja de datos (PDF) - NXP Semiconductors.

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Fabricante

LPC2212

16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC and external memory interface

NXP Semiconductors. 

NXP Semiconductors

4.0 GB

3.75 GB

3.5 GB

3.0 GB

LPC2212/2214

16/32-bit ARM microcontrollers

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

0xFFFF FFFF

0xF000 0000

0xEFFF FFFF

0xE000 0000

0xDFFF FFFF

0xC000 0000

2.0 GB

1.0 GB

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY)

RESERVED ADDRESS SPACE

16 kB ON-CHIP STATIC RAM

0x8000 0000

0x7FFF FFFF

0x7FFF E000

0x7FFF DFFF

0x4000 4000

0x4000 3FFF

0x4000 0000

0x3FFF FFFF

RESERVED ADDRESS SPACE

0.0 GB

256 kB ON-CHIP FLASH MEMORY (LPC2214)

128 kB ON-CHIP FLASH MEMORY (LPC2212)

Fig 3. LPC2212/2214 memory map

0x0004 0000

0x0003 FFFF

0x0002 0000

0x0001 FFFF

0x0000 0000

002aad183

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and

categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt Request (IRQ), and

non-vectored IRQ as defined by programmable settings. The programmable assignment

scheme means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

The FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classified as FIQ, because then

the FIQ service routine can simply start dealing with that device. But if more than one

request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC

that identifies which FIQ source(s) is (are) requesting an interrupt.

LPC2212_2214_4

Product data sheet

Rev. 04 — 3 January 2008

© NXP B.V. 2008. All rights reserved.

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