LH28F800BJB-PTTL90 Ver la hoja de datos (PDF) - Sharp Electronics

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LH28F800BJB-PTTL90

8M (x8/x16) Flash Memory

Sharp Electronics 

LHF80J21

40

6.2.7 Reset Operations

High Z

RY/BY#(R) ("1")

(SR.7) VOL

("0")

VIH

RP#(P)

VIL

tPLPH

(A)Reset During Read Array Mode

High Z

RY/BY#(R) ("1")

(SR.7) VOL

("0")

VIH

RP#(P)

VIL

tPLRZ

tPLPH

(B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration

2.7V

VCC

VIL

VIH

RP#(P)

VIL

t2VPH

(C)RP# rising Timing

Figure 20. AC Waveform for Reset Operation

Reset AC Specifications

Sym.

Parameter

Notes

Min.

Max.

Unit

tPLPH

tPLRZ

RP# Pulse Low Time

RP# Low to Reset during Block Erase, Full Chip Erase,

Word/Byte Write or Lock-Bit Configuration

2

100

1,2

ns

30

µs

t2VPH VCC 2.7V to RP# High

2,3

100

ns

NOTES:

1. If RP# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing,

the reset will complete within 100ns.

2. A reset time, tPHQV, is required from the later of RY/BY#(SR.7) going High Z("1") or RP# going high until outputs are

valid. Refer to AC Characteristics - Read-Only Operations for tPHQV.

3. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range and also

has been in stable there.

Rev. 1.27

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