LH28F800BJHE-PTTL90 Ver la hoja de datos (PDF) - Sharp Electronics
Número de pieza
componentes Descripción
Fabricante
LH28F800BJHE-PTTL90 Datasheet PDF : 47 Pages
| |||
LHF80J03
41
6.2.8 Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Performance(3)
Sym.
Parameter
VCC=2.7V-3.6V, TA=-40°C to +85°C
VCCW=2.7V-3.6V
Notes Min. Typ.(1) Max.
VCCW=11.7V-12.3V
Min. Typ.(1) Max. Unit
tWHQV1
tEHQV1
Word Write Time
Byte Write Time
32K word Block 2
4K word Block 2
64K byte Block 2
33 200
20
µs
36 200
27
µs
31 200
19
µs
8K byte Block
2
32 200
26
µs
Block Write Time
32K word Block 2
1.1
4
0.66
s
(In word mode)
4K word Block 2
0.15 0.5
0.12
s
Block Write Time
64K byte Block 2
2.2
7
1.4
s
(In byte mode)
8K byte Block
2
0.3
1
0.25
s
tWHQV2
tEHQV2
Block Erase Time
32K word Block
64K byte Block
2
4K word Block
8K byte Block
2
1.2
6
0.6
5
0.9
s
0.5
s
Full Chip Erase Time
2
22.8 114
17.5
s
tWHQV3
tEHQV3
Set Lock-Bit Time
2
tWHQV4
tEHQV4
Clear Block Lock-Bits Time
2
tWHRZ1 Word/Byte Write Suspend Latency Time to
tEHRZ1 Read
4
tWHRZ2 Block Erase Suspend Latency Time to
tEHRZ2 Read
4
Latency Time from Block Erase Resume
tERES Command to Block Erase Suspend
5
Command
56 200
1
5
6
15
16 30
42
µs
0.69
s
6
15 µs
16 30 µs
600
600
µs
NOTES:
1. Typical values measured at TA=+25°C and VCC=3.0V, VCCW=3.0V or 12.0V. Assumes corresponding lock-bits are not
set. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. A latency time is required from issuing suspend command(WE# or CE# going high) until RY/BY# going High Z or SR.7
going "1".
5. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter
than tERES and both commands are written repeatedly, a longer time is required than standard block erase until the
completion of the operation.
Rev. 1.27
Share Link: 