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LH28F800BJHE-PBTL90

8M (x8/x16) Flash Memory

Sharp Electronics 

LHF80J05

14

4.8 Block Erase Suspend Command

The Block Erase Suspend command allows block-erase

interruption to read or word/byte write data in another

block of memory. Once the block erase process starts,

writing the Block Erase Suspend command requests that

the WSM suspend the block erase sequence at a

predetermined point in the algorithm. The device outputs

status register data when read after the Block Erase

Suspend command is written. Polling status register bits

SR.7 and SR.6 can determine when the block erase

operation has been suspended (both will be set to "1").

RY/BY# will also transition to High Z. Specification

tWHRZ2 defines the block erase suspend latency.

When Block Erase Suspend command write to the CUI, if

block erase was finished, the device places read array

mode. Therefore, after Block Erase Suspend command

write to the CUI, Read Status Register command (70H)

has to write to CUI, then status register bit SR.6 should be

checked for places the device in suspend mode.

At this point, a Read Array command can be written to

read data from blocks other than that which is suspended.

A Word/Byte Write command sequence can also be issued

during erase suspend to program data in other blocks.

Using the Word/Byte Write Suspend command (see

Section 4.9), a word/byte write operation can also be

suspended. During a word/byte write operation with block

erase suspended, status register bit SR.7 will return to "0"

and the RY/BY# output will transition to VOL. However,

SR.6 will remain "1" to indicate block erase suspend

status.

The only other valid commands while block erase is

suspended are Read Status Register and Block Erase

Resume. After a Block Erase Resume command is written

to the flash memory, the WSM will continue the block

erase process. Status register bits SR.6 and SR.7 will

automatically clear and RY/BY# will return to VOL. After

the Erase Resume command is written, the device

automatically outputs status register data when read (see

Figure 9). VCCW must remain at VCCWH1/2 (the same

VCCW level used for block erase) while block erase is

suspended. RP# must also remain at VIH. WP# must also

remain at VIL or VIH (the same WP# level used for block

erase). Block erase cannot resume until word/byte write

operations initiated during block erase suspend have

completed.

If the time between writing the Block Erase Resume

command and writing the Block Erase Suspend command

is shorter than tERES and both commands are written

repeatedly, a longer time is required than standard block

erase until the completion of the operation.

4.9 Word/Byte Write Suspend Command

The Word/Byte Write Suspend command allows

word/byte write interruption to read data in other flash

memory locations. Once the word/byte write process

starts, writing the Word/Byte Write Suspend command

requests that the WSM suspend the Word/Byte write

sequence at a predetermined point in the algorithm. The

device continues to output status register data when read

after the Word/Byte Write Suspend command is written.

Polling status register bits SR.7 and SR.2 can determine

when the word/byte write operation has been suspended

(both will be set to "1"). RY/BY# will also transition to

High Z. Specification tWHRZ1 defines the word/byte write

suspend latency.

When Word/Byte Write Suspend command write to the

CUI, if word/byte write was finished, the device places

read array mode. Therefore, after Word/Byte Write

Suspend command write to the CUI, Read Status Register

command (70H) has to write to CUI, then status register

bit SR.2 should be checked for places the device in

suspend mode.

At this point, a Read Array command can be written to

read data from locations other than that which is

suspended. The only other valid commands while

word/byte write is suspended are Read Status Register and

Word/Byte Write Resume. After Word/Byte Write

Resume command is written to the flash memory, the

WSM will continue the word/byte write process. Status

register bits SR.2 and SR.7 will automatically clear and

RY/BY# will return to VOL. After the Word/Byte Write

Resume command is written, the device automatically

outputs status register data when read (see Figure 10).

VCCW must remain at VCCWH1/2 (the same VCCW level

used for word/byte write) while in word/byte write

suspend mode. RP# must also remain at VIH. WP# must

also remain at VIL or VIH (the same WP# level used for

word/byte write).

If the time between writing the Word/Byte Write Resume

command and writing the Word/Byte Write Suspend

command is short and both commands are written

repeatedly, a longer time is required than standard

word/byte write until the completion of the operation.

Rev. 1.27

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