LFECP10E-4T144C Ver la hoja de datos (PDF) - Lattice Semiconductor

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LFECP10E-4T144C

LatticeECP/EC Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeECP/EC Family Data Sheet

grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after

adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block

allows the user to adjust the phase and duty cycle of the CLKOS output.

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated

with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider

is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post

scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-

quency range. The secondary divider is used to derive lower frequency outputs.

Figure 2-11. PLL Diagram

Dynamic Delay Adjustment

LOCK

CLKI

(from routing or

external pin)

Input Clock

Divider

(CLKI)

Delay

Adjust

Voltage

ConVtCroOlled

Oscillator

Post Scalar

Divider

(CLKOP)

Phase/Duty

Select

CLKOS

RST

CLKFB

from CLKOP

(PLL internal),

from clock net

(CLKOP) or

from a user

clock (PIN or logic)

Feedback

Divider

(CLKFB)

Secondary

Clock

Divider

(CLKOK)

CLKOP

CLKOK

Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.

Figure 2-12. PLL Primitive

CLKI

CLKFB

EPLLB

CLKOP

LOCK

RST

CLKI

CLKFB

DDA MODE

DDAIZR

DDAILAG

DDAIDEL[2:0]

EHXPLLB

CLKOP

CLKOS

CLKOK

LOCK

DDAOZR

DDAOLAG

DDAODEL[2:0]

2-10

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