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Número de pieza

componentes Descripción

Fabricante

AD8347

Direct Conversion Quadrature Demodulator

Analog Devices 

AD8347

100pF

LO

200⍀

100pF

LOIN

AD8347

LOIP

Figure 5. Single-Ended LO Drive

Operating the VGA

A three-stage VGA sets the gain in the RF section. Two of the

three stages come before the mixer while the third amplifies the

mixer output. All three stages are driven in parallel. The gain

range of the first RF VGA and that of the second RF VGA

combined with the mixer are both –13 dB to +10 dB. The

gain range of the baseband VGA is –4 dB to +19.5 dB. So the

overall gain range from the RF input to the IMXO/QMXO pins

is –30 dB to approximately +39.5 dB.

The gain of the VGA is set by the voltage on the VGIN pin,

which is a high impedance input. The gain control function

(which is linear-in-dB) and linearity are shown in TPC 1 and

TPC 2 at 1.9 GHz. Note that the sense of the gain control

voltage is negative so as the gain control voltage ranges from 0.2 V

to 1.2 V, the gain decreases from +39.5 dB to –30 dB.

Mixer Output Level and Drive Capability

I & Q channel baseband outputs, IMXO and QMXO are low

impedance outputs (ROUT @ 3 Ω) whose bias level is equal to

VVREF, the voltage on Pin 14. The achievable output level on

IMXO/QMXO is limited by their current drive capability of

1.5 mA max. This would allow for a 600 mV p-p swing into a

200 Ω load. At lower output levels, IMXO and QMXO can

drive smaller load resistances, subject to the same current limit.

These output stages are not, however, designed to drive 50 Ω

loads directly.

Operating the VGA in AGC Mode

While the VGA can be driven by an external source such as a

DAC, the AD8347 has an on-board sum of squares detector

which allows the AD8347 to operate in an automatic leveling

mode. The connections for operating in this mode are shown in

Figure 4. The two mixer outputs are connected to the detector

inputs VDT1 and VDT2. The summed detector output drives

an internal integrator which in turn delivers a gain correction

voltage to the VAGC pin. A 0.1 µF capacitor from VAGC to

ground sets the dominant pole of the integrator circuit. VAGC,

which should be connected to VGIN, adjusts gain until an

internal threshold is reached. This threshold corresponds to a level

at the IMXO/QMXO pins of approximately 8.5 mV rms. This

level will change slightly as a function of RF input power (see

TPC 30). For a CW (sine wave) input this corresponds to

+VS +5V

C6 C5 C7 C8 C9 C10

0.1␮F 100pF 0.1␮F 100pF 0.1␮F 100pF

R19

1k⍀

R20

4k⍀



120mV p-p

1V BIAS

C13

0.1␮F

2.5V

IOPP

3.8V p-p

DIFFERENTIAL

VCM = 2.5V

VPS1

VPS2

VPS3 VREF

IMXO

IOFS IAIN

IOPP

IOPN

C1

100pF

R1

200⍀

C2

100pF

RF

INPUT

ENBL

RFIN

RFIP

VGIN

AD8347

BIAS

CELL

VREF

GAIN

CONTROL

INTERFACE

DET 1

DET 2

VDT1 VAGC VDT2 QMXO

R21

4k⍀

R22

1k⍀

VREF

IOPN

VCMO

PHASE

SPLITTER

2

VREF

QOFS

C14

0.1␮F

120mV p-p

1V BIAS

QAIN

VCMO

PHASE

SPLITTER

1

VCMO

LOIN

LOIP

COM3

COM2

COM3

COM1

QOPP QOPN

C4

100pF

LO INPUT

–8dBm

0.8GHz–2.7GHz

R17

200⍀

34

15

T1

C3 ETC 1-1-13

100pF (M/A-COM)

QOPN

3.8V p-p

DIFFERENTIAL

VCM = 2.5V

QOPP

Figure 6. Adjusting AGC Level to Increase Baseband Amplifier Output Swing

REV. 0

–15–

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