MAX189BCWE Ver la hoja de datos (PDF) - Maxim Integrated
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MAX189BCWE Datasheet PDF : 20 Pages
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+5V, Low-Power, 12-Bit Serial ADCs
SPI and Microwire
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion in progress. Wait until
DOUT goes high or the maximum specified 8.5µs con-
version time. Two consecutive 1-byte reads are
required to get the full 12 bits from the ADC. DOUT out-
put data transitions on SCLK’s falling edge and is
clocked into the µP on SCLK’s rising edge.
The first byte contains a leading 1 and 7 bits of conver-
sion result. The second byte contains the remaining 5
bits and 3 trailing 0s. See Figure 13 for connections
and Figure 14 for timing.
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the
ADC, QSPI allows the minimum number of clock cycles
necessary to clock in the data. The MAX187/MAX189
require 13 clock cycles from the µP to clock out the
12 bits of data with no trailing 0s (Figure 15). The maxi-
mum clock frequency to ensure compatibility with QSPI
is 2.77MHz.
Opto-Isolated Interface,
Serial-to-Parallel Conversion
Many industrial applications require electrical isolation
to separate the control electronics from hazardous
electrical conditions, provide noise immunity, or pre-
vent excessive current flow where ground disparities
exist between the ADC and the rest of the system.
Isolation amplifiers typically used to accomplish these
tasks are expensive. In cases where the signal is even-
tually converted to a digital form, it is cost effective to
isolate the input using opto-couplers in a serial link.
The MAX187 is ideal in this application because it
includes both T/H amplifier and voltage reference,
operates from a single supply, and consumes very little
power (Figure 16).
+5V ON THIS SIDE OF
BARRIER MUST BE ISOLATED POWER
+5V
3k
10µF
MAX187
0.1µF
ANALOG
INPUT
1 VDD
2 AIN
4 REF
4.7µF 5 GND
SHDN 3
CS 7
SCLK 8
DOUT 6
3k
470Ω
SIGNAL
GROUND
Figure 16. 12-Bit Isolated ADC
CS/START
6N136
+5V
SCLK/INPUT CLOCK
8
1
7
2 200Ω
6
3
5
4
6N136
74HC04
8
1
7
2 200Ω 74HC04
14 SER
QH 7
QG 6
74HC595 QF 5
11 SCK
QE 4
QD 3 D11 (MSB)
12 RCK
QC 2 D10
QB 1 D9
10 SCLR
QA
15
16
D8
+5V
6
3
5
4
13 8
0.1µF
6N136
1
8
2
7
3
6
4
5
9
14 SER
QH′
QH 7 D7
QG 6 D6
8.2k
74HC595 QF 5 D5
11 SCK
QE 4 D4
12
RCK
QD 3 D3
QC 2 D2
QB 1 D1
+5V 10 SCLR
QA 15 D0(LSB)
16
+5V
13 8
0.1µF
16 ______________________________________________________________________________________
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