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MAX189ACWE(2012) Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza
componentes Descripción
Fabricante
MAX189ACWE
(Rev.:2012)
MaximIC
Maxim Integrated MaximIC
MAX189ACWE Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MAX187/ MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Detailed Description
Converter Operation
The MAX187/MAX189 use input track/hold (T/H) and suc-
cessive approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. No exter-
nal hold capacitor is needed for the T/H. Figures 3a and
3b show the MAX187/MAX189 in their simplest configu-
ration. The MAX187/MAX189 convert input signals in the
0V to VREF range in 10µs, including T/H acquisition time.
The MAX187’s internal reference is trimmed to 4.096V,
while the MAX189 requires an external reference. Both
devices accept external reference voltages from +2.5V to
VDD. The serial interface requires only three digital lines,
SCLK, CS, and DOUT, and provides easy interface to
microprocessors (µPs).
Both converters have two modes: normal and shutdown.
Pulling SHDN low shuts the device down and reduces
supply current to below 10µA, while pulling SHDN high or
leaving it floating puts the device into the operational mode.
A conversion is initiated by CS falling. The conversion result
is available at DOUT in unipolar serial format. A high bit,
signaling the end of conversion (EOC), followed by the data
bits (MSB first), make up the serial data stream.
The MAX187 operates in one of two states: (1) internal
reference and (2) external reference. Select internal
reference operation by forcing SHDN high, and external
reference operation by floating SHDN.
Analog Input
Figure 4 illustrates the sampling architecture of the
ADC’s analog comparator. The full-scale input voltage
depends on the voltage at REF.
REFERENCE
Internal Reference
(MAX187 only)
External Reference
ZERO SCALE
0V
0V
FULL SCALE
+4.096V
VREF
For specified accuracy, the external reference voltage
range spans from +2.5V to VDD.
DOUT
3kI
CLOAD = 100pF
DGND
A. HIGH-Z TO VOH AND VOL TO VOH
Figure 1. Load Circuits for DOUT Enable Time
DOUT
3kI
DGND
A. VOH TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
Maxim Integrated
CLOAD = 100pF
DOUT
+5V
3kI
CLOAD = 100pF
DGND
B. HIGH-Z TO VOL AND VOH TO VOL
DOUT
+5V
3kI
CLOAD = 100pF
DGND
B. VOL TO HIGH-Z
  7

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