SAA7165WP Ver la hoja de datos (PDF) - Philips Electronics
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SAA7165WP Datasheet PDF : 28 Pages
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Philips Semiconductors
Video Enhancement and Digital-to-Analog
processor (VEDA2)
Product specification
SAA7165
CHARACTERISTICS
VDDD = 4.5 to 5.5 V; VDDA = 4.75 to 5.25 V; LLC = LL27; MC = CREF = 13.5 MHz; Tamb = 0 to 70 °C; measurements
taken in Fig.14; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Supplies
VDDD1
VDDD2
VDDA1
VDDA2
VDDA3
VDDA4
IDDD
IDDA
supply voltage range (pin 12)
supply voltage range (pin 31)
supply voltage range (pin 32)
supply voltage range (pin 37)
supply voltage range (pin 40)
supply voltage range (pin 42)
supply current (IDDD1 + IDDD2)
supply current (IDDA1 + IDDA4)
for digital part
4.5
5
for digital part
4.5
5
for buffer of DAC 1
4.75
5
for buffer of DAC 2
4.75
5
for buffer of DAC 3
4.75
5
DAC reference voltage 4.75
5
for digital part
−
tbf
for DACs and buffers −
tbf
YUV-bus inputs (pins 4 to 11 and 14 to 21) (see Figs 3 and 4)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
CI
input capacitance
ILI
input leakage current
VI = HIGH
−0.5
−
2.0
−
−
−
−
−
Inputs AP, SP, MC, LLC, HREF and RESET (pins 22 to 27)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
CI
input capacitance
ILI
input leakage current
V24
MC input voltage for LL27
CREF signal on MC input
−0.5
−
2.0
−
VI = HIGH
−
−
−
−
27 MHz data rate
2.0
−
CREF data rate; note 1 −
−
5.5
V
5.5
V
5.25
V
5.25
V
5.25
V
5.25
V
tbf
mA
tbf
mA
+0.8
V
VDDD + 0.5 V
10
pF
4.5
µA
+0.8
V
VDDD + 0.5 V
10
pF
4.5
µA
VDDD + 0.5 V
−
V
I2C-bus SCL and SDA (pins 28 and 29)
VIL
LOW-level input voltage
−0.5
−
VIH
HIGH-level input voltage
3.0
−
II
input current
VI = LOW or HIGH
−
−
VACK
output voltage at acknowledge
(pin 29)
I29 = 3 mA
−
−
I29
output current
during acknowledge 3
−
Digital-to-analog converters (pins 1, 2, 41, 42, 43 and 44)
VDAC
input reference voltage for internal
resistor chains (pin 42)
4.75
5
ICUR
input current (pin 41)
R41-42 = 15 kΩ
−
300
V1,44
reference voltage LOW
pin connected to VSSA1 −
0
CL
external blocking capacitor to
VSSA1 for reference voltage HIGH
(pins 2 and 43)
−
0.1
fLLC
data conversation rate (clock)
Fig.3
−
−
+1.5
V
VDDD + 0.5 V
±10
µA
0.4
V
−
mA
5.25
V
−
µA
−
V
−
µF
36
MHz
1996 Aug 20
13
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