KSZ8841-PMQL(2006) Ver la hoja de datos (PDF) - Micrel

Número de pieza

componentes Descripción

Fabricante

KSZ8841-PMQL
(Rev.:2006)

Single-Port Ethernet MAC Controller with PCI Interface

Micrel 

Micrel, Inc.

KSZ8841-PMQL

Functional Description

The KSZ8841-PMQL is a single chip Fast Ethernet MAC controller consisting of a 10/100 physical layer transceiver

(PHY), a MAC, and a PCI interface unit that controls the KSZ8841-PMQL via a 32 bit/33MHz PCI processor interface.

The KSZ8841-PMQL is fully compliant to the IEEE802.3u standard.

PCI Bus Interface Unit

PCI Bus Interface

The PCI Bus Interface implements PCI v2.2 bus protocols and configuration space. The KSZ8841-PMQL supports bus

master reads and writes to CPU memory, and CPU access to on-chip register space. When the CPU reads and writes

the configuration registers of the KSZ8841-PMQL, it is as a slave. So the KSZ8841-PMQL can be either a PCI bus

master or slave. The PCI Bus Interface is also responsible for managing the DMA interfaces and the host processors

access. Arbitration logic within the PCI Bus Interface unit accepts bus requests from the TXDMA logic and RXDMA

logic.

The PCI bus interface also manages interrupt generation for a host processor.

TXDMA Logic and TX Buffer Manager

The KSZ8841-PMQL supports a multi-frame, multi-fragment DMA gather process. Descriptors representing frames are

built and linked in system memory by a host processor. The TXDMA logic is responsible for transferring the multi-

fragment frame data from the host memory into the TX buffer.

The TXDMA logic monitors the amount of free space in the TX buffer, and uses this value to decide when to request a

TXDMA.

The KSZ8841-PMQL uses 4K bytes of transmit data buffer between the TXDMA logic and transmit MAC. When the

TXDMA logic determines there is enough space available in the TX buffer, the TXDMA logic will move any pending

frame data into the TX buffer. The management mechanism depends on the transmit descriptor list.

RXDMA Logic and RX Buffer Manager

The KSZ8841-PMQL supports a multi-frame, multi-fragment DMA scatter process. Descriptors representing frames are

built and linked in system memory by the host processor. The RXDMA logic is responsible for transferring the frame

data from the RX buffer to the host memory.

The RXDMA logic monitors the number of bytes in the RX buffer. After a number of bytes have been received, the

frame is “visible”.

The KSZ8841-PMQL uses 4K bytes of receive data buffer between the receive MAC and RXDMA logic. The

management mechanism depends on the receive descriptor list.

Power Management

Power down

The KSZ8841-PMQL features a port power-down mode. To save power, the user can power-down this port that is not

in use by setting bit 11 in either P1CR4 or P1MBCR register for this port. To bring the port back up, reset bit 11 in these

registers.

In addition, there is a full chip power-down mode by pulled-down the PWRDN pin 36. When this pin is pulled-down, the

entire chip powers down. Transitioning this pin from pull-down to pull-up results in a power up and chip reset.

Wake-on-LAN

Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the

network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote

administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device

is pre-programmed by the policy owner or other software with information on how to identify wake frames from other

network traffic.

A wake-up event is a request for hardware and/or software external to the network device to put the system into a

powered state (working).

June 2006

14

M9999-061206-1.2

Share Link: