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KB2516

TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER

Samsung 

KB2516 (Preliminary)

TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER

HSYNC

ADC_CK

HSYNCO

td1

tHS_DELAY

tHS_LENGTH

td2

tHS

DENO

tDEN_DELAY

tDEN_LENGTH

td3

td4

tHS

: HSYNCO period

tHS_DELAY : HSYNC input (HSYNC) to HSYNC output (HSYNCO) delay

tHS_LENGTH : HSYNC output (HSYNCO) high duration

tDEN_DELAY : HSYNCO rising edge to DENO rising edge delay

tDEN_LENGTH: Data enable output (DENO) high duration

td1

: ADC_CK rising edge to HSYNCO rising edge delay

td2

: ADC_CK rising edge to HSYNCO falling edge delay

td3

: ADC_CK rising edge to DENO rising edge delay

td4

: ADC_CK rising edge to DENO falling edge delay

Figure 6. HSYNCO and DENO Output Timing Diagram

• Divider register (DIV)

This register controls the PLL frequency. Default value is 1664 (680H)

tHS = T × DIV (T: VCO clock period, 512 ≤ DIV ≤ 4096)

• HSYNCO duty control (HSD)

tHS_LENGTH = HSD × T - td1 + td2, HSD ≥ 5

• DENO signal delay control (DED)

tDEN_DELAY = DED × T - td1 + td3, DED ≥ 5

• DENO duty control (DEL)

tDEN_LENGTH = (DIV - DED - DEL) × T - td3 + td4, DEL ≥ 5

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