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RTL8305S Ver la hoja de datos (PDF) - Realtek Semiconductor

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RTL8305S Datasheet PDF : 24 Pages
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RTL8305S
The other active-low input pin is P4FLCTRL#, which determines if flow control algorithm is enabled through the MII port.
(default P4FLCTRL#=1 )
If P4FLCTRL#=0 and P4DPXSTA#=0, 802.3x flow control packets will flow through the MII port.
If P4FLCTRL#=0 and P4DPXSTA#=1, a back-pressure algorithm will be implemented through the MII port.
If P4FLCTRL#=1, no flow control algorithm is performed on the MII port.
All three input pins, P4DPXSTA#, P4SPDSTA#, and P4FLCTRL#, have no effect when P4LNKSTA#=1.
It is important to note that the MRXD[3:0] pins in MII/SNI PHY mode are MTXD[3:0] for MII MAC mode, and vice versa.
Also the same for pin MRXDV vs. MTXEN, and pin MRXC vs. MTXC.
NOTE: There are no MRXER, MTXER, MCRS and SMI (MDC/MDIO) pins for MII signaling. Because of the absence of
MCRS, system designers can wire MRXDV directly to CRS and RXDV of the opposite chip.
R TL8305S
x
Floating=High
P4Mode[1]
x
Floating=High
P4Mode[0]
x
Floating=High
P4LnkSta#
x
Floating=High
P4SpdSta#
x
Floating=High
P4DupSta#
x
Floating=High
P4FlCtrl#
x
Floating=High
EnP4Led
x
Not Used
SelMiiMac#
59 MRXC/MTXC
60 MRXDV/MTXEN
67~61 MRXD[3:0]/MTXD[3:0]
4
51 MTXC/MRXC
52 MTXEN/MRXDV
57-54 MTXD[3:0]/MRXD[3:0]
4
58 COL
A llshould be floating
5 UTP Mode (Default five port switch application)
For general cases, most of the option pins should be floating (=High=Enable), except EnBrdCtrl. This means that EnBrdCtrl
should be pulled down (=Low=Disable) for normal applications.
2002/02/19
14
Rev. 1.2

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