GRM32DR61E106K Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

GRM32DR61E106K

4-Channel Integrated LCD Supply

Intersil 

A2

FAULT

VDD

0.4V

A1

0.2V

ISL97650B

VSUP

VREF

C20

R6

820pF

40k

FBN

C19

100pF

R7

328k

0.5MHz

STOP

CLK

PWM

EN

CONTROL

M2

NOUT

C12

220nF

M1

PGND

D2

D3

VOFF (-8V)

C13

470nF

FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM

The maximum VOFF output voltage of a single stage charge pump is:

VOFF_MAX(2x) = – VSUP + VDIODE + 2 • IOUT • (RON(NOUT)H + RON(NOUT)L)

(EQ. 21)

R6 and R7 in the “Typical Application Diagram” on page 10

determine VOFF output voltage. as shown in Equation 22:

VOFF

=

VF

B

N

•

⎛

⎝

1

+

RR-----76--⎠⎞

–

VR

EF

•

⎛

⎝

RR-----76--⎠⎞

(EQ. 22)

Improving Charge Pump Noise Immunity

Depending on PCB layout and environment, noise pick-up at

the FBP and FBN inputs, which may degrade load regulation

performance, can be reduced by the inclusion of capacitors

across the feedback resistors (e.g. in the Application

Diagram, C21 and C22 for the positive charge pump). Set

R6•C20 = R7•C19 with C19 ~ 100pF.

VON Slice Circuit

The VON Slice Circuit functions as a three way multiplexer,

switching the voltage on COM between ground, DRN and SRC,

under control of the start-up sequence and the CTL pin.

During the start-up sequence, COM is held at ground via an

NDMOS FET, with ~1k impedance. Once the start-up

sequence has completed, CTL is enabled and acts as a

multiplexer control such that if CTL is low, COM connects to

DRN through a 30Ω internal MOSFET, and if CTL is high,

COM connects to POUT internally via a 5Ω MOSFET.

The slew rate of start-up of the switch control circuit is mainly

restricted by the load capacitance at COM pin as shown in

Equation 23:

Δ--Δ---V-t- = -(--R----i---|-|---R--V---L-g--)---×-----C-----L-

(EQ. 23)

Where Vg is the supply voltage applied to DRN or voltage at

POUT, which range is from 0V to 36V. Ri is the resistance

between COM and DRN or POUT including the internal

MOSFET rDS(On), the trace resistance and the resistor

inserted, RL is the load resistance of the switch control

circuit, and CL is the load capacitance of the switch control

circuit.

In the Typical Application Circuit, R10, R11 and C15 give the

bias to DRN based on Equation 24:

VDRN

=

-V----O----N------⋅---R----1----1---+----A----V----D-----D------⋅---R----1----0--

R10 + R11

(EQ. 24)

And R12 can be adjusted to adjust the slew rate.

16

FN6748.1

March 22, 2010

Share Link: