GRM32DR61E106K Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

GRM32DR61E106K

4-Channel Integrated LCD Supply

Intersil 

0.5MHz

0.9V

+

-

VREF

+

-

CONTROL

ERROR

FB

ISL97650B

VSUP

M2

M4

VSUP

M1

D3

D2

D1

VSUP

M3

M5

External Connections

and Components

x2 Mode

x3 Mode

C1-

Both

C7

C1+

POUT

C14

C2+

C8

C2-

C21

R8

FBP

C22

R9

FIGURE 16. VON FUNCTION DIAGRAM

In voltage doubler configuration, the maximum VON is as

given by Equations 18, 19 and 20:

VON_MAX(2x) = 2 • (VSUP – VDIODE) – 2 • IOUT • (2 • RONH + RONL)

(EQ. 18)

For Voltage Tripler:

VON_MAX(3x)= 3 • (VSUP – VDIODE) – 2 • IOUT • (3 • RONH + 2 • RONL )

(EQ. 19)

VON output voltage is determined by Equation 20:

VON

=

VF

BP

•

⎛

⎜1

⎝

+

R-R----89- ⎠⎟⎞

(EQ. 20)

Negative Charge Pump Design Consideration

The negative charge pump consists of an internal switcher

M1, M2 which drives external steering diodes D2 and D3 via

a pump capacitor (C12) to generate the negative VOFF

supply. An internal comparator (A1) senses the feedback

voltage on FBN and turns on M1 for a period up to half a

CLK period to maintain V(FBN) in regulated operation at

0.2V. External feedback resistor R6 is referenced to VREF.

Faults on VOFF which cause VFBN to rise to more than 0.4V,

are detected by comparator (A2) and cause the fault

detection system to start a fault ramp on CDLY pin which will

cause the chip to power down if present for more than the

time TFD (see "Electrical Specifications" table on page 2 and

also Figure 16.

15

FN6748.1

March 22, 2010

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