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IS61LPD25632T

256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

IS61SPD25632T/D IS61LPD25632T/D

IS61SPD25636T/D IS61LPD25636T/D

IS61SPD51218T/D IS61LPD51218T/D

ISSI ®

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

Symbol Parameter

-166*

-150

-133

-100

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Unit

fMAX Clock Frequency

— 166

— 150

— 133

— 100

MHz

tKC

Cycle Time

6

—

6.7 —

7.5 —

10

—

ns

tKH

Clock High Pulse Width

2.3 —

2.5 —

2.8 —

3

—

ns

tKL

Clock Low Pulse Width

2.3 —

2.5 —

2.8 —

3

—

ns

tKQ

Clock Access Time

— 3.5

— 3.8

—

4

—

5

ns

tKQX(1) Clock High to Output Invalid

1.5 —

1.5 —

1.5 —

1.5 —

ns

tKQLZ(1,2) Clock High to Output Low-Z

0

—

0

—

0

—

0

—

ns

tKQHZ(1,2) Clock High to Output High-Z

— 3.5

— 3.8

—

4

—

5

ns

tOEQ Output Enable to Output Valid

— 3.5

— 3.8

—

4

—

5

ns

tOELZ(1,2) Output Enable to Output Low-Z

0

—

0

—

0

—

0

—

ns

tOEHZ(1,2) Output Enable to Output High-Z

—

3.2

— 3.8

—

4

—

5

ns

tAS

Address Setup Time

1.5 —

1.5 —

1.5 —

2

—

ns

tSS

Address Status Setup Time

1.5 —

1.5 —

1.5 —

2

—

ns

tWS Write Setup Time

1.5 —

1.5 —

1.5 —

2

—

ns

tCES Chip Enable Setup Time

1.5 —

1.5 —

1.5 —

2

—

ns

tAVS Address Advance Setup Time

1.5 —

1.5 —

1.5 —

2

—

ns

tAH

Address Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tSH

Address Status Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tWH Write Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tCEH Chip Enable Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tAVH Address Advance Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

*This speed available only in SPD version

Note:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

Integrated Silicon Solution, Inc. — 1-800-379-4774

13

PRELIMINARY INFORMATION Rev. 00A

04/17/01

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