IS41LV16257C-35KLI Ver la hoja de datos (PDF) - Integrated Silicon Solution
Número de pieza
componentes Descripción
Fabricante
IS41LV16257C-35KLI Datasheet PDF : 20 Pages
| |||
IS41C16257C
IS41LV16257C
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
-35
Min. Max.
-60
Min. Max.
tach
Column-Address Setup Time to CAS
15
—
15 —
Precharge during WRITE Cycle
toeh
OE Hold Time from WE during
8
—
15 —
READ-MODIFY-WRITE cycle(18)
tds
Data-In Setup Time(15, 22)
0
—
0
—
tdh
Data-In Hold Time(15, 22)
6
—
10 —
trwc READ-MODIFY-WRITE Cycle Time
80
—
140 —
trwd RAS to WE Delay Time during
46
—
80 —
READ-MODIFY-WRITE Cycle(14)
tcwd
CAS to WE Delay Time(14, 20)
tawd
Column-Address to WE Delay Time(14)
25
—
30
—
36 —
49 —
tpc
Fast Page Mode READ or WRITE
Cycle Time(24)
14
—
25 —
trasp RAS Pulse Width
tcpa
Access Time from CAS Precharge(15)
35 100K
—
20
60 100K
— 35
tprwc READ-WRITE Cycle Time(24)
45
—
60 —
toff
Output Buffer Turn-Off Delay from
3
10
3
15
CAS or RAS(13,15,19, 29)
twhz
Output Disable Delay from WE
3
10
3
15
tclch Last CAS going LOW to First CAS
10
—
10 —
returning HIGH(23)
tcsr
CAS Setup Time (CBR REFRESH)(30, 20)
tchr
CAS Hold Time (CBR REFRESH)(30, 21)
tord
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
8
—
8
—
0
—
10 —
10 —
0
—
tref
Refresh Period (512 Cycles)
—
8
—
8
tt
Transition Time (Rise or Fall)(2, 3)
2
50
2
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vdd = 5.0V ±10%)
One TTL Load and 50 pF (Vdd = 3.3V ±10%)
Input timing reference levels: Vih = 2.0V, Vil = 0.8V (Vdd = 5.0V ±10%);
Vih = 2.0V, Vil = 0.8V (Vdd = 3.3V ±10%)
Output timing reference levels: Voh = 2.4V, Vol = 0.4V (Vdd = 5V ±10%, 3.3V ±10%)
Integrated Silicon Solution, Inc.
9
Rev. 00A
04/092010
Share Link: 