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IS41LV16257C-35KLI

256Kx16 4Mb DRAM WITH FAST PAGE MODE

Integrated Silicon Solution 

IS41C16257C

IS41LV16257C

ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter

Test Condition Vdd/Speed Min. Max. Unit

Idd1

Stand-by Current: TTL

RAS, LCAS, UCAS ≥ Vih

Com. 5V

—

3.3V —

4 mA

4

Ind. 5V

—

5

3.3V —

5

Idd2

Stand-by Current: CMOS

RAS, LCAS, UCAS ≥ Vdd – 0.2V

5V

—

3.3V —

1 mA

1

Idd3

Operating Current:

RAS, LCAS, UCAS,

-35

Random Read/Write(2,3,4)

Address Cycling, trc = trc (min.)

-60

Average Power Supply Current

— 230 mA

— 170

Idd4

Operating Current:

RAS = Vil, LCAS, UCAS,

-35

Fast Page Mode(2,3,4)

Cycling tpc = tpc (min.)

-60

Average Power Supply Current

— 220 mA

— 160

Idd5

Refresh Current:

RAS Cycling, LCAS, UCAS ≥ Vih

-35

RAS-Only(2,3)

trc = trc (min.)

-60

Average Power Supply Current

— 230 mA

— 170

Idd6

Refresh Current:

RAS, LCAS, UCAS Cycling

CBR(2,3,5)

trc = trc (min.)

Average Power Supply Current

-35

— 230 mA

-60

­— 170

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper de-

vice operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each fast page cycle.

5. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc.

7

Rev.  00A

04/092010

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