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IS41LV16257C-35TLI

256Kx16 4Mb DRAM WITH FAST PAGE MODE

Integrated Silicon Solution 

IS41C16257C

IS41LV16257C

Functional Description

The IS41C16257C/IS41LV16257C is a CMOS DRAM

optimized for high-speed bandwidth, low-power applications.

During READ or WRITE cycles, each bit is uniquely

addressed through the 18 address bits. These are entered

nine bits (A0-A8) at a time. The row address is latched

by the Row Address Strobe (RAS). The column address

is latched by the Column Address Strobe (CAS). RAS is

used to latch the first nine bits and CAS is used to latch

the latter nine bits.

The IS41C16257C/IS41LV16257C has two CAS controls,

LCAS and UCAS. The LCAS and UCAS inputs internally

generate a CAS signal functioning in an identical manner to

the single CAS input on the other 256K x 16 DRAMs. The

key difference is that each CAS controls its corresponding

I/O tristate logic (in conjunction with OE and WE and RAS).

LCAS controls I/O0 - I/O7 and UCAS controls I/O8 - I/

O15.

The IS41C16257C/IS41LV16257C CAS function is

determined by the first CAS (LCAS or UCAS) transitioning

LOW and the last transitioning back HIGH. The two CAS

controls give the IS41C16257C/IS41LV16257C both BYTE

READ and BYTE WRITE cycle capabilities.

Memory Cycle

A memory cycle is initiated by bringing RAS LOW and it is

terminated by returning both RAS and CAS HIGH.To ensure

proper device operation and data integrity any memory

cycle, once initiated, must not be ended or aborted before

the minimum tras time has expired. A new cycle must not

be initiated until the minimum precharge time trp, tcp has

elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH.The column

address must be held for a minimum time specified by tar.

Data Out becomes valid only when trac, taa, tcac and toea

are all satisfied. As a result, the access time is dependent

on the timing relationships between these parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and

WE, whichever occurs last. The input data must be valid at

or before the falling edge of CAS or WE, whichever occurs

last.

Refresh Cycle

To retain data, 512 refresh cycles are required in each

8 ms period. There are two ways to refresh the memory:

1. By clocking each of the 512 row addresses (A0 through

A8) with RAS at least once every 8 ms. Any read, write,

read-modify-write or RAS-only cycle refreshes the ad-

dressed row.

2. Using a CAS-before-RAS refresh cycle.CAS-before-RAS

refresh is activated by the falling edge of RAS, while

holding CAS LOW. In CAS-before-RAS refresh cycle,

an internal 9-bit counter provides the row addresses and

the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data access

or device selection is allowed. Thus, the output remains in

the High-Z state during the cycle.

Power-On

After application of the Vdd supply, an initial pause of

200 µs is required followed by a minimum of eight

initialization cycles (any combination of cycles containing

a RAS signal).

During power-on, it is recommended that RAS track with

Vdd or be held at a valid Vih to avoid current surges.

Integrated Silicon Solution, Inc.

5

Rev.  00A

04/092010

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