IS41C16256C(2013) Ver la hoja de datos (PDF) - Integrated Silicon Solution

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IS41C16256C
(Rev.:2013)

256Kx16 4Mb DRAM WITH EDO PAGE MODE

Integrated Silicon Solution 

IS41C16256C

IS41LV16256C

ELECTRICAL CHARACTERISTICS(1)

(Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Vdd

Max. Unit

Idd1

Stand-by Current: TTL

RAS, LCAS, UCAS ≥ Vih

5V

3.3V

2 mA

2 mA

Idd2

Stand-by Current: CMOS

RAS, LCAS, UCAS ≥ Vdd – 0.2V

5V

3.3V

1 mA

1 mA

Idd3

Operating Current:

RAS, LCAS, UCAS,

5V

Random Read/Write(2,3,4)

Address Cycling, trc = trc (min.)

3.3V

Average Power Supply Current

150 mA

90 mA

Idd4

Operating Current:

RAS = Vil, LCAS, UCAS,

EDO Page Mode(2,3,4)

Cycling tpc = tpc (min.)

Average Power Supply Current

5V

3.3V

60 mA

30 mA

Idd5

Refresh Current:

RAS Cycling, LCAS, UCAS ≥ Vih

RAS-Only(2,3)

trc = trc (min.)

Average Power Supply Current

5V

3.3V

90 mA

60 mA

Idd6

Refresh Current:

RAS, LCAS, UCAS Cycling

5V

CBR(2,3,5)

trc = trc (min.)

3.3V

Average Power Supply Current

90 mA

60 mA

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc.

7

Rev. A

1/31/2013

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