IS41C16256C(2013) Ver la hoja de datos (PDF) - Integrated Silicon Solution

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IS41C16256C
(Rev.:2013)

256Kx16 4Mb DRAM WITH EDO PAGE MODE

Integrated Silicon Solution 

IS41C16256C

IS41LV16256C

TRUTH TABLE(5)

Function

RAS LCAS UCAS WE OE Address tr/tc I/O

Standby

H

X

X

X

X

X

High-Z

Read: Word

L

L

L

H

L

ROW/COL Dout

Read: Lower Byte

L

L

H

H

L

ROW/COL Lower Byte, Dout

Upper Byte, High-Z

Read: Upper Byte

L

H

L

H

L

ROW/COL Lower Byte, High-Z

Upper Byte, Dout

Write: Word (Early Write)

L

L

L

L

X

ROW/COL Din

Write: Lower Byte (Early Write)

L

L

H

L

X

ROW/COL Lower Byte, Din

Upper Byte, High-Z

Write: Upper Byte (Early Write)

L

H

L

L

X ROW/COL Lower Byte, High-Z

Upper Byte, Din

Read-Write(1,2)

L

EDO Page-Mode Read(2) 1st Cycle: L

2nd Cycle: L

Any Cycle: L

EDO Page-Mode Write(1) 1st Cycle: L

2nd Cycle: L

L

H→L

H→L

L→H

H→L

H→L

L

H→L

H→L

L→H

H→L

H→L

H→L

H

H

H

L

L

L→H

L

L

L

X

X

ROW/COL

ROW/COL

NA/COL

NA/NA

ROW/COL

NA/COL

Dout, Din

Dout

Dout

Dout

Din

Din

EDO Page-Mode

Read-Write(1,2)

Hidden Refresh

RAS-Only Refresh

1st Cycle: L

2nd Cycle: L

Read(2)  L→H→L

Write(1,3)  L→H→L

L

H→L

H→L

L

L

H

H→L

H→L

L

L

H

H→L

H→L

H

L

X

L→H

L→H

L

X

X

ROW/COL

NA/COL

ROW/COL

ROW/COL

ROW/NA

Dout, Din

Dout, Din

Dout

Dout

High-Z

CBR Refresh(4)

H→L

L

L

H

X

X

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. Early write only.

4. At least one of the two CAS signals must be active (LCAS or UCAS).

5. Commands valid only after proper intialization.

High-Z

4

Integrated Silicon Solution, Inc.

Rev. A

1/31/2013

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