HYB314100BJ-70 Ver la hoja de datos (PDF) - Infineon Technologies

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componentes Descripción

Fabricante

HYB314100BJ-70

4M×1-Bit Dynamic RAM

Infineon Technologies 

HYB 514100BJ-50/-60

4M × 1 DRAM

VIH

RAS

VIL

VIH

CAS

VIL

VIH

A0 - A10

VIL

VIH

WE

VIL

DO

VOH

(Output) VOL

t RP

t RPG

t CP

t CSR

t WTS

t OFF

"H" or "L"

t RC

t RAS

t CHR

t WTH

Hi Z

t RP

t RPC

t CRP

t ASR

Row

Address

SPT03024

Test Mode Entry

Test Mode

The HYB 514100BJ is organized 4 194 304 words by 1-bit but can internally be configured as

524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode.

In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading,

all bits are equal, the data output pin indicates a “1”. If any of the bits differ, the data output pin

indicates a “0”. In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode

is exited by any refresh operation which is not a WE, CAS-before-RAS cycle. Addresses A10R,

A10C and A0C do not care during Test Mode.

Semiconductor Group

20

1998-10-01

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