IR1153S Ver la hoja de datos (PDF) - International Rectifier

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IR1153S

FIXED 22.2kHz FREQUENCY, µPFC ONE CYCLE CONTROL IC WITH BROWN-OUT PROTECTION

International Rectifier 

IR1153S

IR1153 General Description

Programmable Soft Start

The soft start process controls the rate of rise of the

voltage feedback loop error signal thus providing a

linear increase of the RMS input current that the

PFC converter will admit. The soft start time is

essentially controlled by voltage error amplifier

compensation components selected and is

therefore user programmable to some degree

based on desired voltage feedback loop crossover

frequency.

Gate Drive Capability

The gate drive output stage of the IC is a totem

pole driver with 750mA peak current drive

capability. The gate drive is internally clamped at

14.1V (Typ). Gate drive buffer circuits (especially

cost-effective base-followers) can be easily driven

with the GATE pin of the IC to suit any system

power level.

System Protection Features

IR1153 protection features include Brown-out

protection (BOP), Open-loop protection (OLP),

Overvoltage protection (OVP), Cycle-by-cycle peak

current limit (IPK LIMIT), Soft-current limit and VCC

under voltage lock-out (UVLO).

- BOP is based on direct input line sensing using a

resistor divider/RC filter network. If BOP pin falls

below the Brown-out protection threshold VBOP, a

Brown-out situation is immediately detected the

following response is executed - the gate drive

pulse is disabled, VCOMP is actively discharged

and IC is pushed into Stand-by Mode. The IC re-

enters normal operation only after BOP pin

exceeds VBOP(EN). During start-up the IC is held in

Stand-by Mode until this pin exceeds VBOP(EN).

- OLP is activated whenever the VFB pin voltage

falls below VOLP threshold. Once open loop is

detected the following response is immediately

executed - the gate drive is immediately disabled,

VCOMP is actively discharged and the IC is

pushed into Stand-by mode. There is no voltage

hysteresis associated with this feature. During

start-up the IC is held in Stand-by Mode until VFB

exceeds VOLP.

- The OVP pin is a dedicated pin for overvoltage

protection that safeguards the system even if

there is a break in the VFB feedback loop due to

resistor divider failure etc. An overvoltage fault is

triggered when OVP pin voltage exceeds the VOVP

threshold of 106%VREF. The response of the IC

is to immediately terminate the gate drive output

and hold it in that state. The gate drive is re-

enabled only after OVP pin voltage drops below

VOVP(RST) threshold of 103% VREF. The exact

voltage level at which overvoltage protection is

triggered can be programmed by the user by

carefully designing the OVP pin resistor divider. It

is recommended NOT to set the OVP voltage

trigger limit less than 106% of DC bus voltage,

since this can endanger the situation where the

OVP reset limit will be less than the DC bus

voltage regulation point – in this condition the

voltage loop can become unstable.

- Soft-current limit is an output voltage fold-back

type protection feature encountered when the

PFC converter input current exceeds to a point

where the Vm voltage saturates. As mentioned

earlier, the amplitude of input current is directly

proportional to Vm, the error voltage of the

feedback loop. Vm is clamped to a certain

maximum voltage inside the IC (given by

VCOMP,EFF parameter in datasheet). If the input

current causes the Vm voltage to saturate at its

maximum value, then any further increase in input

current will cause the duty cycle to droop which

immediately forces the VOUT voltage of the PFC

converter to fold-back. Since the highest current

is at the peak of the AC sinusoid, the droop in

duty cycle commences at the peak of the AC

sinusoid when the soft-current limit is

encountered. In most converters, the design of

the current sense resistor is performed based on

soft-current limit (i.e. Vm saturation) and at the

system condition which demands highest input

current (minimum VAC & maximum POUT).

- Cycle-by-cycle peak current limit protection

instantaneously turns-off the gate output

whenever the ISNS pin voltage exceeds VISNS(PK)

threshold in magnitude. The gate drive is held in

the low state as long as the overcurrent condition

persists. The gate drive is re-enabled when the

magnitude of ISNS pin voltage falls below the

VISNS(PK) threshold. This protection feature

incorporates a leading edge blanking circuit to

improve noise immunity.

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